參數(shù)資料
型號(hào): AD-C0838CCN
廠商: National Semiconductor Corporation
元件分類: 串行ADC
英文描述: 8-Bit Serial I/O A/D Converters with Multiplexer Options
中文描述: 8位串行I /辦公自動(dòng)化/ D轉(zhuǎn)換器多路復(fù)用選項(xiàng)
文件頁數(shù): 5/32頁
文件大?。?/td> 678K
代理商: AD-C0838CCN
Converter and Multiplexer Electrical Characteristics
The following specifications apply for
V
CC
= V+ = V
REF
= 5V, V
REF
V
CC
+0.1V, T
A
= T
j
= 25C, and f
CLK
= 250 kHz unless otherwise specified.
Boldface limits
apply from T
MIN
to T
MAX
.
Parameter
Conditions
CIWM Devices
BCV, CCV, CCWM, BCN
and CCN Devices
Typ
Tested
(Note 12)
Limit
(Note 13)
Typ
Tested
Limit
(Note 13)
Design
Limit
(Note 14)
Design
Limit
(Note 14)
Units
(Note 12)
CONVERTER AND MULTIPLEXER CHARACTERISTICS
I
ON
, On Channel Leakage
Current (Note 9)
On Channel=0V,
Off Channel=5V
On Channel=5V,
Off Channel=0V
0.2
1
+0.2
+1
0.2
1
μA
+0.2
+1
μA
DIGITAL AND DC CHARACTERISTICS
V
IN(1)
, Logical “1” Input
Voltage (Min)
V
IN(0)
, Logical “0” Input
Voltage (Max)
I
IN(1)
, Logical “1” Input
Current (Max)
I
IN(0)
, Logical “0” Input
Current (Max)
V
OUT(1)
, Logical “1” Output
Voltage (Min)
V
CC
=5.25V
2.0
2.0
2.0
V
V
CC
=4.75V
0.8
0.8
0.8
V
V
IN
=5.0V
0.005
1
0.005
1
1
μA
V
IN
=0V
0.005
1
0.005
1
1
μA
V
CC
=4.75V
I
OUT
=360 μA
I
OUT
=10 μA
V
CC
=4.75V
I
OUT
=1.6 mA
V
OUT
=0V
V
OUT
=5V
V
OUT
=0V
2.4
4.5
0.4
2.4
4.5
0.4
2.4
4.5
0.4
V
V
V
V
OUT(0)
, Logical “0” Output
Voltage (Max)
I
OUT
, TRI-STATE Output
Current (Max)
I
SOURCE
, Output Source
Current (Min)
I
SINK
, Output Sink Current (Min)
I
CC
, Supply Current (Max)
ADC0831, ADC0834,
ADC0838
ADC0832
0.1
0.1
14
3
3
6.5
0.1
0.1
14
3
+3
7.5
3
+3
6.5
μA
μA
mA
V
OUT
=V
CC
16
8.0
16
9.0
8.0
mA
0.9
2.5
0.9
2.5
2.5
mA
Includes Ladder
Current
2.3
6.5
2.3
6.5
6.5
mA
AC Characteristics
The following specifications apply for V
CC
= 5V, t
r
= t
f
= 20 ns and 25C unless otherwise specified.
Typ
Tested
Limit
(Note 13)
10
Design
Limit
(Note 14)
Limit
Units
Parameter
Conditions
(Note 12)
f
CLK
, Clock Frequency
Min
Max
kHz
kHz
1/f
CLK
%
%
ns
400
t
C
, Conversion Time
Clock Duty Cycle
(Note 10)
t
SET-UP
, CS Falling Edge or
Data Input Valid to CLK
Rising Edge
t
HOLD
, Data Input Valid
after CLK Rising Edge
Not including MUX Addressing Time
8
Min
Max
40
60
250
90
ns
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參數(shù)描述
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