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參數(shù)資料
| 型號(hào)： | ACT-D1M96S-020F20C |
| 廠商： | Aeroflex Inc. |
| 英文描述： | ACT-D1M96S High Speed 96 MegaBit 3.3V Synchronous DRAM Multichip Module |
| 中文描述： | 行為D1M96S高速96兆位同步DRAM 3.3V的多芯片模塊 |
| 文件頁(yè)數(shù)： | 4/14頁(yè) |
| 文件大?。?/td> | 105K |
| 代理商： | ACT-D1M96S-020F20C |
第1頁(yè)第2頁(yè)第3頁(yè)當(dāng)前第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)
Aeroflex Circuit Technology
SCD3369-1 REV C 5/31/00 Plainview NY (516) 694-6700
4
Auto Refresh (REFR)
Before performing a REFR, both banks of all 6 chips must be deactivated (placed in precharge). To
enter a REFR command, RAS and CAS must be low and WE must be high upon the rising edge of
CLK (see Table 1). The refresh address is generated internally such that, after 4096 REFR commands,
both banks of all 6 chips of the ACT-D1M96S have been refreshed. The external address and bank
select (A11) are ignored. The execution of a REFR command automatically deactivates both banks
upon completion of the internal auto-refresh cycle, allowing consecutive REFR-only commands to be
executed, if desired, without any intervening DEAC commands. The REFR commands do not
necessarily have to be consecutive, but all 4096 must be completed before
t
REF
expires.
Power Up Initialization
Device initialization should be performed after a power up to the full V
CC
level. After power is
established, a 200μs interval is required (with no inputs other than CLK). After this interval, both banks
of the device must be deactivated. Eight REFR commands must be performed, and the mode register
must be set to complete the device initialization.
General Information for AC Timing Measurements
All specifications referring to READ commands are also valid for READ-P commands unless otherwise
noted. All specifications referring to WRT commands are also valid for WRT-P commands unless
otherwise noted. All specifications referring to consecutive commands are specified as consecutive
commands for the same bank unless otherwise noted.
Note: For all pin references in the General Description, both sections apply. For example, A11 signals
also apply for BA11 signals.
For additional Detail Information regarding the operation of the individual chip (MT48LC1M16A1) see
Micron’s 524,288-WORD BY 16-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS
MEMORY Datasheet Revision 8/99 or contact the Aeroflex Sales Department.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ACT-D1M96S-020F20I | ACT-D1M96S High Speed 96 MegaBit 3.3V Synchronous DRAM Multichip Module |
| ACT-D1M96S-020F20M | ACT-D1M96S High Speed 96 MegaBit 3.3V Synchronous DRAM Multichip Module |
| ACT-D1M96S-020F20Q | ACT-D1M96S High Speed 96 MegaBit 3.3V Synchronous DRAM Multichip Module |
| ACT-D1M96S-020F20T | ACT-D1M96S High Speed 96 MegaBit 3.3V Synchronous DRAM Multichip Module |
| ACT-D1M96S | ACT-D1M96S High Speed 96 MegaBit 3.3V Synchronous DRAM Multichip Module |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ACT-D1M96S-020F20I | 制造商:AEROFLEX 制造商全稱:AEROFLEX 功能描述:ACT-D1M96S High Speed 96 MegaBit 3.3V Synchronous DRAM Multichip Module |
| ACT-D1M96S-020F20M | 制造商:AEROFLEX 制造商全稱:AEROFLEX 功能描述:ACT-D1M96S High Speed 96 MegaBit 3.3V Synchronous DRAM Multichip Module |
| ACT-D1M96S-020F20Q | 制造商:AEROFLEX 制造商全稱:AEROFLEX 功能描述:ACT-D1M96S High Speed 96 MegaBit 3.3V Synchronous DRAM Multichip Module |
| ACT-D1M96S-020F20T | 制造商:AEROFLEX 制造商全稱:AEROFLEX 功能描述:ACT-D1M96S High Speed 96 MegaBit 3.3V Synchronous DRAM Multichip Module |
| ACT-D2M32A-090F18C | 制造商:AEROFLEX 制造商全稱:AEROFLEX 功能描述:ACT-F2M32A High Speed 64 Megabit Sector Erase FLASH Multichip Module |
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