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參數(shù)資料
| 型號： | ACT-D1M96S-020F20C |
| 廠商： | Aeroflex Inc. |
| 英文描述： | ACT-D1M96S High Speed 96 MegaBit 3.3V Synchronous DRAM Multichip Module |
| 中文描述： | 行為D1M96S高速96兆位同步DRAM 3.3V的多芯片模塊 |
| 文件頁數(shù)： | 3/14頁 |
| 文件大?。?/td> | 105K |
| 代理商： | ACT-D1M96S-020F20C |
Aeroflex Circuit Technology
SCD3369-1 REV C 5/31/00 Plainview NY (516) 694-6700
3
Two-Bank Column-Access Operation
The availability of two banks allows the access
of data from random starting columns between
banks at a higher rate of operation. After
activating each bank with a row address (ACTV
command), A11 can be used to alternate READ
or WRT commands between the banks to
provide gapless accesses at the CLK frequency,
provided all specified timing requirements are
met.
Bank Deactivation (Precharge)
Both banks can be deactivated (placed in
precharge) simultaneously by using the DCAB
command. A single bank can be deactivated by
using the DEAC command. The DEAC command
is entered identically to the DCAB command
except that A10 must be low and A11 used to
select the bank to be precharged as shown in
Table 1. A bank can be deactivated automatically
by using A10 during a read or write command. If
A10 is held high during the entry of a read or write
command, the accessed bank (selected by A11)
is deactivated automatically upon completion of
the access burst. If A10 is held low during the
entry of a read or write command, that bank
remains active following the burst. The read and
write commands with automatic deactivation are
signified as READ-P and WRT-P.
Chip Select (CS)
CS can be used to select or deselect the
ACT-D1M96S for command entry, which might
be
required
for
decoding. If CS is held high on the rising edge of
CLK (DESL command), the device does not
respond to RAS, CAS, or WE until the device is
selected again by holding CS low on the rising
edge of CLK. Any other valid command can be
entered simultaneously on the same rising CLK
edge of the select operation. The device can be
selected/deselected on a cycle-by-cycle basis
(see Table 1 and Table 2). The use of CS does
not affect an access burst that is in progress; the
DESL command can only restrict RAS, CAS, and
WE input to the ACT-D1M96S.
Data Mask
The mask command or its opposite, the data-in
enable (ENBL) command (see Table 3), is
performed on a cycle-by-cycle basis to gate any
data cycle within a write burst. DQML controls
DQ
0-7
, DQ
16-23
, DQ
32-39
, DQ
48-55
, DQ
64-71
,
multiple-memory-device
DQ
80-87
and DQMU controls DQ
8-15
, DQ
24-31
,
DQ
40-47
, DQ
56-63
, DQ
72-79
, and DQ
88-95
. The
application of DQMx to a write burst has no
latency (
n
DID
= 0 cycle). During a write burst, if
DQMx is held high on the rising edge of CLK, the
data-input is ignored on that cycle.
CLK-Suspend
For normal device operation, CKE should be held
high to enable CLK. If CKE goes low during the
execution of a READ (READ-P) or WRT
(WRT-P) operation, the DQ bus occurring at the
immediate next rising edge of CLK is frozen at its
current state, and no further inputs are accepted
until CKE returns high. This is known as a
CLK-suspend operation, and its execution
indicates a HOLD command. The device
resumes operation from the point when it was
placed in suspension, beginning with the second
rising edge of CLK after CKE returns high.
Setting the Mode Register
The ACT-D1M96S contains a mode register in
each chip that must be programmed with the
CAS latency, the burst type, and the burst length.
This
is
accomplished
mode-register set (MRS) command with the
information entered on the address lines A0-A9.
A logic 0 must be entered on A7 and A8, but A10
and A11 are don’t-care entries for the
ACT-D1M96S. When A9 = 0, the write-burst
length is defined by A0-A2. Figure 1 shows the
valid combinations for a successful MRS
command. Only valid addresses allow the mode
register to be changed. If the addresses are not
valid, the previous contents of the mode register
remain unaffected. The MRS command is
executed by holding RAS, CAS, and WE low and
the input mode word valid on A0-A9 on the rising
edge of CLK (see Table 1). The MRS command
can be executed only when both banks are
deactivated.
Refresh
The ACT-D1M96S must be refreshed at intervals
not exceeding t
REF
(see timing requirements) or
data cannot be retained. Refresh can be
accomplished by performing a read or write
access to every row in both banks or 4096
auto-refresh (REFR) commands. Regardless of
the method used, refresh must be accomplished
before t
REF
has expired.
by
executing
a
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相關(guān)代理商/技術(shù)參數(shù) |
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| ACT-D1M96S-020F20I | 制造商:AEROFLEX 制造商全稱:AEROFLEX 功能描述:ACT-D1M96S High Speed 96 MegaBit 3.3V Synchronous DRAM Multichip Module |
| ACT-D1M96S-020F20M | 制造商:AEROFLEX 制造商全稱:AEROFLEX 功能描述:ACT-D1M96S High Speed 96 MegaBit 3.3V Synchronous DRAM Multichip Module |
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