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| 型號： | ACT-700SC-150F24Q |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁數(shù)： | 10/24頁 |
| 文件大?。?/td> | 227K |
| 代理商： | ACT-700SC-150F24Q |
Aeroflex Circuit Technology
SCD7000 REV A 3/16/00 Plainview NY (516) 694-6700
10
Cache Locking
The ACT 7000SC allows critical code or data
fragments to be locked into the primary and
secondary caches. The user has complete control
over what locking is performed with cache line
granularity. For instruction and data fragments in the
primaries, locking is accomplished by setting either or
both of the cache lock enable bits in the CP0 ECC
register, specifying the set via a field in the CP0 ECC
register, and then executing either a load instruction
or a Fill_I cache operation for data or instructions
respectively. Only two sets are lockable within each
cache: set A and set B. Locking within the secondary
works identically to the primaries using a separate
secondary lock enable bit and the same set selection
field. As with the primaries, only two sets are lockable:
sets A and B. Table 7 summarizes the cache locking
capabilities.
Table 7 – Cache Locking Control
Cache Management
To improve the performance of critical data
movement operations in the embedded environment,
the ACT 7000SC significantly improves the speed of
operation of certain critical cache management
operations as compared with the R5000 and R4000
families.
In
particular,
Hit-Write-back-Invalidate and Hit-Invalidate cache
operations has been improved in some cases by an
order of magnitude over that of the earlier families.
Table 8 compares the ACT 7000SC with the R4000
and R5000 processors.
Table 8 – Penalty Cycle
the
speed
of
the
For the Hit-Dirty case of Hit-Writeback-Invalidate, if
the writeback buffer is full from some previous cache
eviction then n is the number of cycles required to
empty the write-back buffer. If the buffer is empty then
n is zero.
The penalty value is the number of processor
cycles beyond the one cycle required to issue the
instruction that is required to implement the operation.
Table 6 – Cache Attributes
Attribute
Instruction
Data
Secondary
Size
16KB
16KB
256KB
Associativity
4-way
4-way
4-way
Replacement Algorithm.
cyclic
cyclic
cyclic
Line size
32 byte
32 byte
32 byte
Index
vAddr
11..0
vAddr
11..0
pAddr
15..0
Tag
pAddr
35..12
pAddr
35..12
pAddr
35..16
Write policy
n.a.
write-back, write-through
block write-back, bypass
read policy
n.a.
non-blocking (2 outstanding) non-blocking (data only, 2
outstanding)
read order
critical word first
critical word first
critical word first
write order
NA
sequential
sequential
miss restart following:
complete line
first double (if waiting for
data)
n.a.
Parity
per word
per byte
per doubleword
Cache
Lock
Enable
Set Select
Activate
Primary I
ECC[27]
ECC[28]=
0
→
A
ECC[28]=
1
→
B
Fill_I
Primary D
ECC[26]
ECC[28]=
0
→
A
ECC[28]=
1
→
B
Load/Store
Secondary
ECC[25]
ECC[28]=
0
→
A
ECC[28]=
1
→
B
Fill_I or
Load/Store
Operation
Condition
Penalty
ACT 7000S
C
R4000/R500
0
Hit-Writebac
k-Invalidate
Miss
0
7
Hit-Clean
3
12
Hit-Dirty
3+n
14+n
Hit-Invalidate Miss
0
7
Hit
2
9
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| ACT-700SC-150F24T | Microprocessor |
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| ACT-700SC-200F17I | Microprocessor |
| ACT-700SC-200F17M | Microprocessor |
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相關(guān)代理商/技術(shù)參數(shù) |
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| ACT-700SC-150F24T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
| ACT-700SC-200F17C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
| ACT-700SC-200F17I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
| ACT-700SC-200F17M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
| ACT-700SC-200F17Q | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
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