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參數(shù)資料
| 型號： | ACT-5271SC-150F10I |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁數(shù)： | 1/11頁 |
| 文件大?。?/td> | 237K |
| 代理商： | ACT-5271SC-150F10I |
eroflex Circuit Technology – MIPS TurboEngines For The Future SCD5271SC REV A 2/2/01
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Footprint Compatible with Aeroflex’s original ACT-4431SC 1MB Secondary Cache MCM in the
280 lead Ceramic Quad Flat Pack (CQFP)
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QED RM5271 Dual Issue superscalar microprocessor - can issue one integer and one
floating-point instruction per cycle
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Max system clock – 25MHz, Max Secondary Cache (SC) clock 75MHz, Max pipeline 150MHz
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High performance system interface compatible with R4400
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Internal PLL generates selectable 2x/3x SC bus speed operation vs external system bus
speed
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Generates R4400 style system clocks
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CPU cycle rate buffering FIFO implemented in FPGA
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64-bit multiplexed system address/data bus for optimum price/performance
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High performance write protocols maximize uncached write bandwidth
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Operates at processor clock multipliers 2, 2.5 & 3
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Integrated on-chip Primary Caches
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32KB instruction - 2 way set associative
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32KB data - 2 way set associative
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Virtually indexed, physically tagged
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Write-back and write-through on per page basis
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Pipeline restart on first double for data cache misses
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Integrated in-module Secondary Cache
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2MB shared write-through
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4-128Kx36 Synchronous SRAM and 1-64Kx18 Tag RAM
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Integrated memory management unit
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Fully associative joint TLB (shared by I and D translations)
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48 dual entries map 96 pages
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Variable page size (4KB to 16MB in 4x increments)
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High-performance floating point unit
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Single cycle repeat rate for common single precision operations and some double precision
operations
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Two cycle repeat rate for double precision multiply and double precision combined
multiply-add operations
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Single cycle repeat rate for single precision combined multiply-add operation
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MIPS IV instruction set
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Floating point multiply-add instruction increases performance in signal processing and
graphics applications
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Conditional moves to reduce branch frequency
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Index address modes (register + register)
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Embedded application enhancements
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Specialized DSP integer Multiply-Accumulate instruction and 3 operand multiply instruction
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I and D cache locking by set
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Optional dedicated exception vector for interrupts
Microprocessor with 2MB Secondary Cache
ACT-5271SC Multichip Module
Features
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ACT-5271SC-150F10M | Microprocessor |
| ACT-5271SC-150F10T | Microprocessor |
| ACT-7000SC-266F17C | ACT 7000SC 64-Bit Superscaler Microprocessor |
| ACT-7000SC-266F17I | ACT 7000SC 64-Bit Superscaler Microprocessor |
| ACT-7000SC-266F24I | ACT 7000SC 64-Bit Superscaler Microprocessor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ACT-5271SC-150F10M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
| ACT-5271SC-150F10T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
| ACT529 K59B WAF | 制造商:ON Semiconductor 功能描述: |
| ACT530SMX-2 | 制造商:ACT 制造商全稱:Advanced Crystal Technology 功能描述:2/4 pad, high quality, low aging 5x3.2mm SMD |
| ACT530SMX-4 | 制造商:ACT 制造商全稱:Advanced Crystal Technology 功能描述:2/4 pad, high quality, low aging 5x3.2mm SMD |
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