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參數(shù)資料
| 型號： | ACPM-7886-TR1 |
| 元件分類： | 放大器 |
| 英文描述： | 2010 MHz - 2025 MHz RF/MICROWAVE NARROW BAND MEDIUM POWER AMPLIFIER |
| 封裝： | 4.0 X 4.0 MM, LEAD FREE, SMT, 10 PIN |
| 文件頁數(shù)： | 14/14頁 |
| 文件大?。?/td> | 339K |
| 代理商： | ACPM-7886-TR1 |
9
Lead Free Reow Prole General Guidelines
i. Ramp 1
Ramp to 100°C. Maximum slope for this zone is limited to
2°C/sec. Faster heating with ramp higher than 2°C may
result in excessive solder balling and slump.
ii. Preheat
Preheat setting should range from 100 to 150°C over a
period of 60 to 120 seconds depending on the charac-
teristics of the PCB components and the thermal charac-
teristics of the oven. If possible, do not prolong preheat
as it will cause excessive oxidation to occur to the solder
powder surface.
iii. Ramp 2
The time in this zone should be kept below 35 seconds
to reduce the risk of ux exhaustion. The ramp up rate
should be 2°C/sec from 150°C to re-ow at 217°C. It is
important that the ux medium retains its activity during
this phase to ensure the complete coalescence of the
solder particles during re-ow.
iv. Reow
The peak reow temperature is calculated by adding
~32°C to the melting point of the alloy. Lead free solder
paste melts at 218°C and peak reow temperature is
218°C + 32°C = 250°C (±5°C). Note that total time over
218°C is critical and should typically be 60 – 150 seconds.
This period determines the appearance of the solder
joints. Excessive time above reow may cause a dull nish
and charred of ux residues. Insucient time above
reow may lead to poor wetting and improperly fused
(cloudy) ux residues.
Figure 3. PCB land pattern
Figure 4. Stencil outline drawing
Figure 5. Combined PCB and stencil layouts
v. Cooling
Maximum slope for cooling is limited to 3°C/sec. More
rapid cooling may cause solder joints crack while cooling
at a slower rate will increase the likelihood of a crystalline
appearance on the solder joints (dull nish).
PCB Design Guidelines
The recommended ACPM-7886 PCB land pattern is
shown in Figure 3. The substrate is coated with solder
mask between the I/O and conductive paddle to protect
the gold pads from short circuit that is caused by solder
bleeding / bridging.
Stencil Design Guidelines
A properly designed solder screen or stencil is required
to ensure optimum amount of solder paste is deposited
onto the PCB pads. The recommended stencil layout is
shown in Figure 4. The stencil has a solder paste deposi-
tion opening that is approximately 80% of the PCB pad.
Reducing the stencil opening can potentially generate
more voids. On the other hand, stencil openings larger
than 100% will lead to excessive solder paste smear or
bridging across the I/O pads or conductive paddle to
adjacent I/O pads. Considering the fact that solder paste
thickness will directly aect the quality of the solder
joint, a good choice is to use laser cut stencil composed
of 0.100mm (4 mils) or 0.127mm (5 mils) thick stainless
steel which is capable of producing the required ne
stencil outline. The combined PCB and stencil layout is
shown in Figure 5.
(dimensions in mm)
2.1
0.85
(PIT
CH)
0.375
0.55
0.3
0.55
0.375
1.68
0.44
0.64
0.44
0.85
3.12
0.41
2.1
1.68
0.55
Stencil
Opening
0.44
0.55
0.44
3.9
3.12
3.9
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