參數(shù)資料
型號(hào): ACH16543DGG
廠商: NXP SEMICONDUCTORS
元件分類: 通用總線功能
英文描述: JT 13C 13#22D PIN PLUG
中文描述: ALVC/VCX/A SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56
封裝: 6.10 MM, PLASTIC, MO-153EE, SOT-364-1, TSSOP-56
文件頁數(shù): 3/20頁
文件大?。?/td> 89K
代理商: ACH16543DGG
1999 Nov 23
3
Philips Semiconductors
Product specification
16-bit D-type registered transceiver; 3-state
74ALVCH16543
QUICK REFERENCE DATA
Ground = 0; T
amb
= 25
°
C; t
r
= t
f
= 2.5 ns
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W).
P
D
= C
PD
×
V
CC2
×
f
i
+
Σ
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
C
L
= output load capacitance in pF;
f
o
= output frequency in MHz;
V
CC
= supply voltage in Volts;
Σ
(C
L
×
V
CC2
×
f
o
) = sum of outputs.
The condition is V
I
= GND to V
CC
.
2.
ORDERING INFORMATION
PINNING
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
propagation delay nA
n
, nB
n
to nB
n
, nA
n
C
L
= 50 pF;
V
CC
= 3.3 V
3.8
ns
C
I
C
PD
input capacitance
power dissipation capacitance per latch
4.0
pF
notes 1 and 2
outputs enabled
outputs disabled
44
14
pF
pF
OUTSIDE NORTH
AMERICA
NORTH
AMERICA
PACKAGE
TEMPERATURE
RANGE
40 to +85
°
C
PINS
PACKAGE
MATERIAL
CODE
74ALVCH16543DGG
ACH16543 DGG
56
TSSOP
plastic
SOT364-1
PIN
SYMBOL
DESCRIPTION
1 and 28
2 and 27
3 and 26
4, 11, 18, 25, 32, 39, 46 and 53
5, 6, 8, 9, 10, 12, 13 and 14
7, 22, 35 and 50
15, 16, 17, 19, 20, 21, 23 and 24
29 and 56
30 and 55
31 and 54
33, 34, 36, 37, 38, 40, 41 and 42
43, 44, 45, 47, 48, 49, 51 and 52
1OE
AB
, 2OE
AB
1LE
AB
, 2LE
AB
1E
AB
, 2E
AB
GND
1A
0
to 1A
7
V
CC
2A
0
to 2A
7
2OE
BA
, 1OE
BA
2LE
BA
, 1LE
AB
2E
BA
, 1E
BA
2B
7
to 2B
0
1B
7
to 1B
0
output enable A-to-B for register 1 or 2
latch enable A-to-B for register 1 or 2
A-to-B enable for register 1 or 2
ground (0 V)
data inputs/outputs
DC supply voltage
data inputs/outputs
output enable B-to-A for register 1 or 2
latch enable B-to-A for register 1 or 2
B-to-A enable for register 1 or 2
data inputs/outputs
data inputs/outputs
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