參數(shù)資料
型號： ACH16543DGG
廠商： NXP SEMICONDUCTORS
元件分類： 通用總線功能
英文描述： JT 13C 13#22D PIN PLUG
中文描述： ALVC/VCX/A SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56
封裝： 6.10 MM, PLASTIC, MO-153EE, SOT-364-1, TSSOP-56
文件頁數(shù)： 2/20頁
文件大?。?/td> 89K
代理商： ACH16543DGG
1999 Nov 23
2
Philips Semiconductors
Product specification
16-bit D-type registered transceiver; 3-state
74ALVCH16543
FEATURES
In accordance with JEDEC standard no 8-1A
CMOS low power consumption
Direct interface with TTL levels
MULTIBYTE
flow-through pin-out architecture
16-bit transceiver with D-type latch
Combines 16245 and 16373 type functions in one chip
Back-to-back registers for storage
Output drive capability 50
transmission lines at 85
°
C
Separate controls for data flow in each direction
All data inputs have bus hold
3-state non-inverting outputs for bus oriented
applications
Current drive
±
24 mA at 3.0 V.
DESCRIPTION
The 74ALVCH16543 is a dual octal registered transceiver.
Each section contains two sets of D-type latches for
temporary storage of the data flow in either direction.
Separate latch enable (nLE
AB
, nLE
BA
) and output enable
(nOE
AB
, nOE
BA
) inputs are provided for each register to
permit independent control in either direction of the data
flow.
The ‘16543’ contains two sections each consisting of two
sets of eight D-type latches with separate inputs and
controls for each set. For data flow from A to B, for
example, the A-to-B enable (nE
AB
, where n equals 1 or 2)
inputsmustbeLOWinordertoenterdatafromnA
0
to nA
7
,
or take data from nB
0
to nB
7
, as indicated in the function
table. With nE
AB
LOW, a LOW signal on the A-to-B latch
enable (nLE
AB
) input makes the A-to-B latches
transparent; a subsequent LOW-to-HIGH transition of the
nLE
AB
signal stores the A data into the latches. With nE
AB
and nOE
AB
both LOW, the 3-state B output buffers are
active and display the data present at the output of the
A latches. Similarly, the nE
BA
, nLE
BA
and nOE
BA
signals
control the data flow from B-to-A.
Active bus hold circuitry is provided to hold unused or
floating data inputs at a valid logic level.
FUNCTION TABLE
See note 1.
Note
1.
XX = AB for A-to-B direction, BA for B-to-A direction;
H = HIGH voltage level; L = LOW voltage level;
h = HIGH state must be present one set-up time before the LOW-to-HIGH transition of nLE
AB
, nLE
BA
, nE
AB
or nE
BA
;
l = LOW state must be present one set-up time before the LOW-to-HIGH transition of nLE
AB
, nLE
BA
, nE
AB
or nE
BA
;
X = don’t care; NC = no change;
↑
= LOW-to-HIGH level transition;
Z = high-impedance OFF-state.
INPUTS
OUTPUTS
STATUS
nOE
XX
H
X
L
L
L
L
L
L
L
nE
XX
X
H
↑
↑
L
L
L
L
L
nLE
XX
X
X
L
L
↑
↑
L
L
H
nB
n
, nA
n
X
X
h
l
h
l
H
L
X
Z
Z
Z
Z
H
L
H
L
NC
disabled
disabled
disabled and latch
latch and display
transparent
hold
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