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參數資料
| 型號： | ACD2204S8P1 |
| 廠商： | ANADIGICS INC |
| 元件分類： | 上/下變頻器 |
| 英文描述： | RF/MICROWAVE DOWN CONVERTER |
| 封裝： | S8, MO-137AF, SSOP-28 |
| 文件頁數： | 20/20頁 |
| 文件大?。?/td> | 350K |
| 代理商： | ACD2204S8P1 |
PRELIMINARY DATA SHEET - Rev 1.0
04/2003
9
ACD2204
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Main Divider Programming
The main divider register for each synthesizer
consists of seven A counter bits, eleven B counter
bits, two program mode bits and the two register
select bits, as shown in Table 10. The main divider
divide ratio, N, is determined by the values in the A
and B counters. The eleven B Counter bits and
allowed values are shown in Table 11, and the seven
A Counter bits and allowed values are shown in
Table 10: Main Divider Registers
Table 12: Main Divider A Counter Bits
Notes:
B > A, A < P
LSB
MSB
Table 11: Main Divider B Counter Bits
Notes:
B > A, Divide ratios less than 3 are prohibited.
Table 12. Note that there are some limitations on
the ranges of the values for each counter.
Pulse Swallow Function
The VCO output frequency for the local oscillator is
computed using the following equation; the
variables are defined in Table 13:
fVCO = N x fOSC/R, where N = [(P x B) + A]
Table 13: Variable Definitions
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