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參數(shù)資料
| 型號： | ACD2204S8P1 |
| 廠商： | ANADIGICS INC |
| 元件分類： | 上/下變頻器 |
| 英文描述： | RF/MICROWAVE DOWN CONVERTER |
| 封裝： | S8, MO-137AF, SSOP-28 |
| 文件頁數(shù)： | 19/20頁 |
| 文件大小： | 350K |
| 代理商： | ACD2204S8P1 |
8
PRELIMINARY DATA SHEET - Rev 1.0
04/2003
ACD2204
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LOGIC PROGRAMMING
Notes:
Divide ratios less than 3 are prohibited.
LSB
MSB
Synthesizer Register Programming
The ACD2204 includes two PLL synthesizers. Each
synthesizer contains programmable Reference and
Main dividers, which allow a wide range of local
oscillator frequencies. The 22-bit registers that control
the dividers are programmed via a shared three-wire
bus, consisting of Data, Clock and Enable lines.
The data word for each register is entered serially
in order with the most significant bit (MSB) first and
the least significant bit (LSB) last. The rising edge
of the Clock pulse shifts each data value into the
register. The Enable line must be low for the duration
of the data entry, then set high to latch the data into
the register. (See Figure 4.)
Register Select Bits
The two least significant bits of each register are
register select bits that determine which register is
programmed during a particular data entry cycle.
Table 7 indicates the register select bit settings used
to program each of the available registers.
Table 7: Register Select Bits
Table 9: Reference Divider R Counter Bits
Table 8: Reference Divider Registers
Reference Divider Programming
The reference divider register for each synthesizer
consists of fifteen divider bits, five program mode
bits and the two register select bits, as shown in
Table 8. The fifteen divider bits allow a divide ratio
from 3 to 32767, inclusive, as shown in Table 9.
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相關代理商/技術參數(shù) |
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| ACD2206 | 制造商:ANADIGICS 制造商全稱:ANADIGICS, Inc 功能描述:CATV/TV/VIDEO DOWNCONVERTER WITH DUAL SYNTHESIZER |
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| ACD2206S8P1 | |
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| ACD222URNM | 制造商:Eaton Corporation 功能描述:60A/2P Non-Fusible Non-Metallic AC Disconnect 240V Nema 3R |
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