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參數(shù)資料
| 型號： | ACD2203S8P1 |
| 廠商： | ANADIGICS INC |
| 元件分類： | 衰減器 |
| 英文描述： | CATV/TV/Video Downconverter with Dual Synthesizer |
| 中文描述： | RF/MICROWAVE DOWN CONVERTER |
| 封裝： | S8, MO-137AF, SSOP-28 |
| 文件頁數(shù)： | 15/24頁 |
| 文件大?。?/td> | 618K |
| 代理商： | ACD2203S8P1 |
PRELIMINARY DATA SHEET - Rev 1.3
12/2003
15
ACD2203
Synthesizer Programming Example
The following example for programming the two synthesizers in the dual PLL details the calculations used
to determine the required value of each bit in all four registers:
Requirements
Desired CATV input channel: “HHH” - 499.25 MHz picture carrier (501 MHz digital channel center frequency)
(Second) IF picture carrier output frequency: 45.75 MHz (44 MHz digital channel center frequency)
First IF frequency: 1087.75 MHz (recommended)
Phase detector comparison frequency for down converter (also tuning increment): 62.5 KHz
Phase detector comparison frequency for up converter: 250 KHz
Crystal reference oscillator frequency: 4 MHz
Calculation of Reference Divider Values
The value for each reference divider is calculated by dividing the reference oscillator frequency by the desired
phase detector comparison frequency:
R = f
OSC
/ f
PD
For the down converter, the 4 MHz crystal oscillator frequency and the 62.5 KHz phase detector comparison
frequency are used to yield R
PLL2
= 4 MHz / 62.5 KHz = 64, and so the bit values for the down converter
R counter are R
PLL2
= 000000001000000.
For the up converter, the 4 MHz crystal oscillator frequency and the 250 KHz phase detector comparison
frequency are used to yield R
PLL1
= 4 MHz / 250 KHz = 16, and so the bit values for the up converter R counter
are R
PLL1
= 000000000010000.
Calculation of Main Divider Values
The values for the A and B counters are determined by the desired VCO output frequency for the local
oscillator and the phase detector comparison frequency:
N = f
VCO
/ f
PD
B = trunc(N / P)
A = N - (B x P)
The down converter local oscillator frequency will be 1087.75 MHz - 45.75 MHz = 1042 MHz in this example.
The main divider ratio for the down converter, then, is N
PLL2
= 1042 MHz / 62.5 KHz = 16672. Since P = 64 in the
ACD2203, B
PLL2
= trunc(16672 / 64) = 260, and A
PLL2
= 16672 - (260 x 64) = 32. These results give bit values
of B
PLL2
= 00100000100 and A
PLL2
= 0100000 for the B and A counters.
The up converter local oscillator frequency will be 499.25 MHz + 1087.75 MHz = 1587 MHz in this example.
Therefore, N
PLL1
= 1587 MHz / 250 KHz = 6348, B
PLL1
= trunc(6348 / 64) = 99, and A
PLL1
= 6348 - (99 x 64) = 12.
These results give bit values of B
PLL1
= 00001100011 and A
PLL1
= 0001100 for the B and A counters.
Phase Detector Polarity
If the VCO for the up converter has a negative slope, the phase detector polarity for PLL1 should be negative,
and D1
PLL1
= 1. If the VCO for the down converter has a positive slope, the phase detector polarity for PLL2
should be positive, and D1
PLL2
= 0.
In summary, for this example, the four register programming words are shown in Tables 17 and 18 on the
following page.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ACD2204 | 制造商:ANADIGICS 制造商全稱:ANADIGICS, Inc 功能描述:CATV/TV/Video Downconverter with Dual Synthesizer |
| ACD2204S&P0 | 制造商:ANADIGICS 制造商全稱:ANADIGICS, Inc 功能描述:CATV/TV/Video Downconverter with Dual Synthesizer |
| ACD2204S&P1 | 制造商:ANADIGICS 制造商全稱:ANADIGICS, Inc 功能描述:CATV/TV/Video Downconverter with Dual Synthesizer |
| ACD2204S8P0 | 制造商:Rochester Electronics LLC 功能描述: 制造商:ANADIGICS Inc 功能描述: |
| ACD2204S8P1 | 制造商:ANADIGICS 制造商全稱:ANADIGICS, Inc 功能描述:CATV/TV/Video Downconverter with Dual Synthesizer |
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