參數(shù)資料
型號(hào)： ACD2203S8P1
廠商： ANADIGICS INC
元件分類： 衰減器
英文描述： CATV/TV/Video Downconverter with Dual Synthesizer
中文描述： RF/MICROWAVE DOWN CONVERTER
封裝： S8, MO-137AF, SSOP-28
文件頁(yè)數(shù)： 12/24頁(yè)
文件大小： 618K
代理商： ACD2203S8P1
12
PRELIMINARY DATA SHEET - Rev 1.3
12/2003
ACD2203
allow a wide range of output frequencies. The 24-bit
registers that control the dividers and other functions
are each segmented into three 8-bit data words, and
are programmed via the two-wire interface.
Register Select Bits
The two least significant bits of each register are
register select bits that determine which register is
programmed during a particular data entry cycle.
Table 8 indicates the register select bit settings used
to program each of the available registers.
N
I
P
N
O
S
E
G
,
1
A
T
L
O
V
A
)
1
Y
R
A
N
I
B
(
C
1
S
A
2
S
A
X
E
H
L
A
M
I
C
E
D
7
B
6
B
5
B
4
B
3
B
2
B
1
B
0
B
V
S
S
V
8
<
S
A
<
1
1
0
0
0
0
1
0
2
C
4
9
1
V
7
<
S
A
<
V
1
1
1
0
0
0
0
0
0
0
C
2
9
1
V
7
<
S
A
<
V
1
1
1
0
0
0
1
0
0
4
C
6
9
1
V
5
6
<
S
A
<
V
5
1
1
1
0
0
0
0
0
0
0
C
2
9
1
V
<
S
A
<
V
2
D
D
1
1
0
0
0
1
1
0
6
C
8
9
1
Table 7: Address Select Decoding
(T
A
= +25 °C
(1)
, V
DD
= +5 VDC)
Table 8: Register Select Bits
T
C
S
E
L
T
B
E
S
R
O
F
R
E
T
A
S
I
T
G
A
D
E
R
L
N
I
O
I
R
E
T
A
S
N
I
T
S
E
D
A
S
2
S
1
0
0
2
L
L
P
r
e
R
r
d
D
e
c
n
e
R
0
1
2
L
L
P
r
e
R
r
d
D
n
M
1
0
1
L
L
P
r
e
R
r
d
D
e
c
n
e
R
1
1
1
L
L
P
r
e
R
r
d
D
n
M
Main Divider Programming
The main divider register for each synthesizer
consists of seven A counter bits, eleven B counter
bits, two program mode bits and the two register
select bits, as shown in Table 11. The main divider
divide ratio, N, is determined by the values in the A
and B counters. The eleven B Counter bits and
allowed values are shown in Table 12, and the seven
A Counter bits and allowed values are shown in
Table 13. Note that there are some limitations on
the ranges of the values for each counter.
Pulse Swallow Function
The VCO output frequency for the local oscillator is
computed using the following equation; the variables
are defined in Table 14:
f
VCO
= N x f
OSC
/R, where N = [(P x B) + A]
where:
N = [(P x B) + A]
f
is the desired output frequency
B is the divide ratio of the B counter (3 to 2047)
A is the divide ratio of the A counter (0<A<P, A<B)
f
is the frequency of the reference oscillator
R is the divide ratio of the R counter (3 to 32767)
P is the preset modulus of the prescalar (P=64).
Reference Divider Programming
The reference divider register for each synthesizer
consists of fifteen divider bits, five program mode
bits and the two register select bits, as shown in
Table 9. The fifteen divider bits allow a divide ratio
from 3 to 32767, inclusive, as shown in Table 10.
Notes:
(1) Case Temperature is 15 °C higher than Ambient Temperature, when Ambient Temperature is
+25 °C, using the PC Board Layout shown in Figures 24-26.
相關(guān)PDF資料
PDF描述
ACD2204 CATV/TV/Video Downconverter with Dual Synthesizer
ACD2204S&P0 CATV/TV/Video Downconverter with Dual Synthesizer
ACD2204S&P1 CATV/TV/Video Downconverter with Dual Synthesizer
ACD2206 ER 37C 37#16 PIN PLUG
ACF2101 Low Noise, Dual SWITCHED INTEGRATOR
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ACD2204 制造商:ANADIGICS 制造商全稱:ANADIGICS, Inc 功能描述:CATV/TV/Video Downconverter with Dual Synthesizer
ACD2204S&P0 制造商:ANADIGICS 制造商全稱:ANADIGICS, Inc 功能描述:CATV/TV/Video Downconverter with Dual Synthesizer
ACD2204S&P1 制造商:ANADIGICS 制造商全稱:ANADIGICS, Inc 功能描述:CATV/TV/Video Downconverter with Dual Synthesizer
ACD2204S8P0 制造商:Rochester Electronics LLC 功能描述: 制造商:ANADIGICS Inc 功能描述:
ACD2204S8P1 制造商:ANADIGICS 制造商全稱:ANADIGICS, Inc 功能描述:CATV/TV/Video Downconverter with Dual Synthesizer
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*