
PRELIMINARY DATA SHEET - Rev 1.5
04/2008
15
ACD2203
Synthesizer Programming Example
ThefollowingexampleforprogrammingthetwosynthesizersinthedualPLLdetailsthecalculationsusedto
determinetherequiredvalueofeachbitinallfourregisters:
Requirements
DesiredCATVinputchannel:“HHH”-499.25MHzpicturecarrier(501MHzdigitalchannelcenterfrequency)
(Second)IFpicturecarrieroutputfrequency:45.75MHz(44MHzdigitalchannelcenterfrequency)
FirstIFfrequency:1087.75MHz(recommended)
Phasedetectorcomparisonfrequencyfordownconverter(alsotuningincrement):62.5KHz
Phasedetectorcomparisonfrequencyforupconverter:250KHz
Crystalreferenceoscillatorfrequency:4MHz
CalculationofReferenceDividerValues
Thevalueforeachreferencedivideriscalculatedbydividingthereferenceoscillatorfrequencybythedesired
phasedetectorcomparisonfrequency:
R=fOSC/fPD
Forthedownconverter,the4MHzcrystaloscillatorfrequencyandthe62.5KHzphasedetectorcomparison
frequencyareusedtoyieldRPLL2=4MHz/62.5KHz=64,andsothebitvaluesforthedownconverter
RcounterareRPLL2=000000001000000.
Fortheupconverter,the4MHzcrystaloscillatorfrequencyandthe250KHzphasedetectorcomparison
frequencyareusedtoyieldRPLL1=4MHz/250KHz=16,andsothebitvaluesfortheupconverterRcounter
areRPLL1=000000000010000.
CalculationofMainDividerValues
ThevaluesfortheAandBcountersaredeterminedbythedesiredVCOoutputfrequencyforthelocaloscillator
andthephasedetectorcomparisonfrequency:
N=f
VCO/fPD
B=trunc(N/P)
A=N-(BxP)
Thedownconverterlocaloscillatorfrequencywillbe1087.75MHz-45.75MHz=1042MHzinthisexample.
Themaindividerratioforthedownconverter,then,isNPLL2=1042MHz/62.5KHz=16672.SinceP=64in
theACD2203,BPLL2=trunc(16672/64)=260,andAPLL2=16672-(260x64)=32.Theseresultsgivebitvalues
ofBPLL2=00100000100andAPLL2=0100000fortheBandAcounters.
Theupconverterlocaloscillatorfrequencywillbe499.25MHz+1087.75MHz=1587MHzinthisexample.
Therefore,NPLL1=1587MHz/250KHz=6348,BPLL1=trunc(6348/64)=99,andAPLL1=6348-(99x64)=12.
TheseresultsgivebitvaluesofBPLL1=00001100011andAPLL1=0001100fortheBandAcounters.
PhaseDetectorPolarity
IftheVCOfortheupconverterhasanegativeslope,thephasedetectorpolarityforPLL1shouldbenegative,
andD1PLL1=1.IftheVCOforthedownconverterhasapositiveslope,thephasedetectorpolarityforPLL2
shouldbepositive,andD1PLL2=0.
Insummary,forthisexample,thefourregisterprogrammingwordsareshowninTables17and18onthe
followingpage.