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參數(shù)資料
| 型號(hào)： | ACD2203RS8P1 |
| 廠商： | ANADIGICS INC |
| 元件分類： | 上/下變頻器 |
| 英文描述： | RF/MICROWAVE DOWN CONVERTER |
| 封裝： | ROHS COMPLIANT, S8, MO-137AF, SSOP-28 |
| 文件頁數(shù)： | 4/24頁 |
| 文件大?。?/td> | 1607K |
| 代理商： | ACD2203RS8P1 |
12
PRELIMINARY DATA SHEET - Rev 1.5
04/2008
ACD2203
areeachsegmentedintothree8-bitdatawords,and
areprogrammedviathetwo-wireinterface.
Register Select Bits
The two least significant bits of each register are
register select bits that determine which register is
programmed during a particular data entry cycle.
Table8indicatestheregisterselectbitsettingsused
toprogrameachoftheavailableregisters.
Reference Divider Programming
The reference divider register for each synthesizer
Table 7: Address Select Decoding
(TA = +25 °C (1), VDD = +5 VDC)
of sevenA counter bits, eleven B counter bits, two
programmodebitsandthetworegisterselectbits,
asshowninTable11.Themaindividerdivideratio,N,
isdeterminedbythevaluesintheAandBcounters.
The eleven B Counter bits and allowed values are
showninTable12,andthesevenACounterbitsand
allowedvaluesareshowninTable13.Notethatthere
aresomelimitationsontherangesofthevaluesfor
eachcounter.
Pulse Swallow Function
TheVCOoutputfrequencyforthelocaloscillatoris
computedusingthefollowingequation:
fVCO=NxfOSC/R
where:
N=[(PxB)+A]
f
VCOisthedesiredoutputfrequency
BisthedivideratiooftheBcounter(3to2047)
AisthedivideratiooftheAcounter(0<A<P,A<B)
f
OSCisthefrequencyofthereferenceoscillator
RisthedivideratiooftheRcounter(3to32767)
Pisthepresetmodulusoftheprescalar(P=64).
consistsoffifteendividerbits,fiveprogrammodebits
andthetworegisterselectbits,asshowninTable9.
Thefifteendividerbitsallowadivideratiofrom3to
32767,inclusive,asshowninTable10.
Main Divider Programming
Themaindividerregisterforeachsynthesizerconsists
Notes:
(1) Case Temperature is 15 °C higher than Ambient Temperature, when Ambient Temperature is +25
°C, using the PC Board Layout shown in Figures 24-26.
VOLTAGE ON PIN
10, AS
C (BINARY 12)
AS2 AS1
HEX
DECIMAL
B7 B6 B5 B4 B3 B2
B1 B0
VSS<AS<0.8V
1
0
1
0
C2
194
1.1V<AS<1.7V
1
0
C0
192
2.1V<AS<2.7V
1
0
1
0
C4
196
3.15V<AS<3.65V
1
0
C0
192
4.2V<AS<VDD
1
0
1
0
C6
198
Table 8: Register Select Bits
SELECT
BITS
DESTINATION REGISTER FOR
SERIAL DATA
S
2
S
1
0
ReferenceDividerRegisterforPLL2
0
1
MainDividerRegisterforPLL2
1
0
ReferenceDividerRegisterforPLL1
1
MainDividerRegisterforPLL1
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