參數(shù)資料
型號(hào)： ACD2202
廠商： ANADIGICS, Inc.
英文描述： CATV/TV/Video Downconverter with Dual Synthesizer
中文描述： 有線電視/電視/視頻變頻器雙合成
文件頁(yè)數(shù)： 13/24頁(yè)
文件大?。?/td> 550K
代理商： ACD2202
Data Sheet - Rev 2.1
12/2003
13
ACD2202
Table 15: Phase Detector Polarity Selection
Programmable Modes
Each register contains bits set aside for
programming different modes of operation in the
synthesizers. Currently, the only programmable
mode is the polarity of the phase detector in each of
the synthesizers. Bit D1 in each reference divider
register controls this feature. Bits D2 through D5 in
the reference divider registers and bits C1 and C2
in the main divider registers are reserved for future
use, and have no current function. They can be set
Table 14: Phase Detector Polarity Bit
Figure 21: VCO Characteristics
either high or low without affecting synthesizer
performance.
Setting Phase Detector Polarity
Table 14 shows how bit D1 of each reference divider
register controls the polarity of the phase detector
associated with each PLL. The correct setting is
determined by using Table 15 and Figure 21.
Synthesizer Programming Example
The following example for programming the two synthesizers in the ACD2202 details the calculations
used to determine the required value of each bit in all four registers:
Requirements
Desired CATV input channel: “HHH” - 499.25 MHz picture carrier (501 MHz digital channel center frequency)
(Second) IF picture carrier output frequency: 45.75 MHz (44 MHz digital channel center frequency)
First IF frequency: 1087.75 MHz
Phase detector comparison frequency for down converter (also tuning increment): 62.5 KHz
Phase detector comparison frequency for up converter: 250 KHz
Crystal reference oscillator frequency: 4 MHz
Calculation of Reference Divider Values
The value for each reference divider is calculated by dividing the reference oscillator frequency by the desired
phase detector comparison frequency:
R = f
OSC
/ f
PD
For the down converter, the 4 MHz crystal oscillator frequency and the 62.5 KHz phase detector comparison
frequency are used to yield R
PLL2
= 4 MHz / 62.5 KHz = 64, and so the bit values for the down converter
R counter are R
PLL2
= 000000001000000.
S
2
S
1
D
1
0
0
y
P
r
e
D
e
s
a
h
P
2
L
L
P
1
0
y
P
r
e
D
e
s
a
h
P
1
L
L
P
D
1
E
O
T
T
R
A
S
A
C
E
L
O
H
T
P
R
Y
E
D
P
O
E
U
C
T
G
I
V
C
F
S
C
I
)
1
T
S
I
E
R
R
A
R
E
A
E
H
S
(
C
0
e
v
g
e
N
)
e
v
c
1
e
v
o
P
)
e
v
c
(1)
(2)
VCO INPUT VOLTAGE
VCO OUTPUT
FREQUENCY
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ACD2202S8P0 制造商:ANADIGICS 制造商全稱:ANADIGICS, Inc 功能描述:CATV/TV/Video Downconverter with Dual Synthesizer
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