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參數(shù)資料
| 型號： | ACD2202 |
| 廠商： | ANADIGICS, Inc. |
| 英文描述： | CATV/TV/Video Downconverter with Dual Synthesizer |
| 中文描述： | 有線電視/電視/視頻變頻器雙合成 |
| 文件頁數(shù)： | 11/24頁 |
| 文件大?。?/td> | 550K |
| 代理商： | ACD2202 |
Data Sheet - Rev 2.1
12/2003
11
ACD2202
LOGIC PROGRAMMING
Notes:
Divide ratios less than 3 are prohibited.
LSB
MSB
Synthesizer Register Programming
The ACD2202 includes two PLL synthesizers. Each
synthesizer contains programmable Reference and
Main dividers, which allow a wide range of local
oscillator frequencies. The 22-bit registers that control
the dividers are programmed via a shared three-wire
bus, consisting of Data, Clock and Enable lines.
The data word for each register is entered serially
in order with the most significant bit (MSB) first and
the least significant bit (LSB) last. The rising edge
of the Clock pulse shifts each data value into the
register. The Enable line must be low for the duration
of the data entry, then set high to latch the data into
the register. (See Figure 4.)
Register Select Bits
The two least significant bits of each register are
register select bits that determine which register is
programmed during a particular data entry cycle.
Table 7 indicates the register select bit settings used
to program each of the available registers.
Table 7: Register Select Bits
Table 9: Reference Divider R Counter Bits
Table 8: Reference Divider Registers
Reference Divider Programming
The reference divider register for each synthesizer
consists of fifteen divider bits, five program mode
bits and the two register select bits, as shown in
Table 8. The fifteen divider bits allow a divide ratio
from 3 to 32767, inclusive, as shown in Table 9.
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相關(guān)代理商/技術(shù)參數(shù) |
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