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| 型號(hào)： | AC164335 |
| 廠商： | Microchip Technology |
| 文件頁(yè)數(shù)： | 50/285頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | MODULE SKT FOR 10X10 PM3 44TQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 模塊/板類型： | TQFP 插座模塊 |
| 適用于相關(guān)產(chǎn)品： | MPLAB? PM3 |
| 產(chǎn)品目錄頁(yè)面： | 658 (CN2011-ZH PDF) |
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2006 Microchip Technology Inc.
Preliminary
DS70178C-page 141
dsPIC30F1010/202X
12.36 EXTERNAL SYNCHRONIZATION
FEATURES
In large power conversion systems, it is often desir-
able to be able to synchronize multiple power control-
lers to ensure that “beat frequencies” are not
generated within the system, or as a means to ensure
“quiet” periods during which current and voltage mea-
surements can be made.
dsPIC30F202X devices (excluding 28-pin packages)
have input and/or output pins that provide the capabil-
ity to either synchronize the SMPS dsPIC DSC device
with an external device or have external devices syn-
chronized to the SMPS dsPIC DSC. These synchro-
nizing features are enabled via the SYNCIEN and
SYNCOEN bits in the PTCON control register in the
PWM module.
The SYNCPOL bit in the PTCON register selects
whether the rising edge or the falling edge of the
SYNCI signal is the active edge. The SYNCPOL bit in
the PTCON register also selects whether the SYNCO
output pulse is low active or high active.
The SYNCSRC<2:0> bits in the PTCON register
specify the source for the SYNCI signal.
If the SYNCI feature is enabled, the primary time base
counter is reset when an active SYNCI edge is
detected. If the SYNCO feature is enabled, an output
pulse is generated when the primary time base
counter rolls over at the end of a PWM cycle.
The recommended SYNCI pulse width should be more
than 100 nsec. The expected SYNCO output pulse
width will be approximately 100 nsec.
When using the SYNCI feature, it is recommended
that the user program the period register with a period
value that is slightly longer than the expected period of
the external synchronization input signal. This pro-
vides protection in case the SYNCI signal is not
received due to noise or external component failure.
With a reasonable period value programmed into the
PTPER register, the local power conversion process
should remain operational even if the global
synchronization signal is not received.
12.37 CPU LOAD STAGGERING
The SMPS dsPIC DSC has the ability to stagger the
individual trigger comparison operations. This feature
helps to level the processor’s workload to minimize
situations where the processor is overloaded.
Assume a situation where there are four PWM chan-
nels controlling four independent voltage outputs.
Assume further that each PWM generator is operating
at 1000 kHz (1 sec period) and each control loop is
operating at 125 kHz (8 sec).
The TRGDIV<2:0> bits in each TRGCONx register will
be set to ‘111’, which selects that every 8th trigger
comparison match will generate a trigger signal to the
ADC to capture data and begin a conversion process.
If the stagger-in-time feature did not exist, all of the
requests from all of the PWM trigger registers might
occur at the same time. If this “pile-up” were to hap-
pen, some data sample might become stale (outdated)
by the time the data for all four channels can be
processed.
With the stagger-in-time feature, the trigger signals are
spaced out over time (during succeeding PWM peri-
ods) so that all of the data is processed in an orderly
manner.
The ROLL counter is a counter connected to the pri-
mary time base counter. The ROLL counter is incre-
mented each time the primary time base counter
reaches terminal count (period rollover).
The stagger-in-time feature is controlled by the
TRGSTRT<5:0> bits in the TRGCONx registers. The
TRGSTRT<5:0> bits specify the count value of the
ROLL counter that must be matched before an individ-
ual trigger comparison module in each of the PWM
generators can begin to count the trigger comparison
events as specified by the TRGDIV<2:0> bits in the
PWMCONx registers.
So, in our example with the four PWM generators, the
first PWM’s TRGSTRT<5:0> bits would be ‘000’, the
second PWM’s TRGSTRT bits would be set to ‘010’,
the third PWM’s TRGSTRT bits would be set to ‘100’
and the fourth PWM’s TRGSTRT bits would be set to
‘110’. Therefore, over a total of eight PWM cycles, the
four separate control loops could be run each with
their own 2-sec time period.
12.38 EXTERNAL TRIGGER BLANKING
Using the LEB<9:3> bits in the LEBCONx registers,
the PWM module has the capability to blank (ignore)
the external current and Fault inputs for a period of 0
to 1024 nsec. This feature is useful if power transistor
turn-on induced transients make current sensing
difficult at the start of a PWM cycle.
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