參數(shù)資料
型號(hào)： AC164335
廠商： Microchip Technology
文件頁(yè)數(shù)： 43/285頁(yè)
文件大?。?/td> 0K
描述： MODULE SKT FOR 10X10 PM3 44TQFP
標(biāo)準(zhǔn)包裝： 1
模塊/板類型： TQFP 插座模塊
適用于相關(guān)產(chǎn)品： MPLAB? PM3
產(chǎn)品目錄頁(yè)面： 658 (CN2011-ZH PDF)
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2006 Microchip Technology Inc.
Preliminary
DS70178C-page 135
dsPIC30F1010/202X
12.25 Simultaneous PWM Faults and
Current Limits
The current-limit override function, if enabled and
active, forces the PWMxH,L pins to the values speci-
fied by the CLDAT<1:0> bits in the IOCONx registers
UNLESS the Fault function is enabled and active. If the
selected Fault input is active, the PWMxH,L outputs
assume the values specified by the FLTDAT<1:0> bits
in the IOCONx registers.
12.26 PWM Fault and Current-Limit TRG
Outputs To ADC
The Fault and current-limit source selection fields in the
FCLCONx registers (FLTSRC<3:0> and CLSRC<3:0>)
control multiplexers in each PWM generator module.
The control multiplexers select the desired Fault and
current-limit signals for their respective modules. The
selected Fault and current-limit signals are also avail-
able to the ADC module as trigger signals that initiate
ADC sampling and conversion operations.
12.27 PWM Output Override Priority
If the PWM module is enabled, the priority of PWMx pin
ownership is:
1.
PWM Generator (lowest priority)
2.
Output Override
3.
Current-Limit Override
4.
Fault Override
5.
PENx (GPIO/PWM) ownership (highest priority)
If the PWM module is disabled, the GPIO module
controls the PWMx pins.
12.28 Fault and Current-Limit Override
Issues with Dead-Time Logic
The PWMxH and PWMxL outputs are immediately
driven
low
(deasserted)
as
specified
by
the
CLDAT<1:0> and the FLTDAT<1:0> bits when a
current-limit or a Fault event occurs.
The override data is gated with the PWM signals going
into the dead-time logic block, and at the output of the
PWM module, just ahead of the PWM pin output
buffers.
Many applications require fast response to current
shutdown for accurate current control and/or to limit
circuitry damage to Fault currents.
Some applications will set the complementary
PWM
outputs
high
in
synchronous
rectifier
designs when a Fault or current-limit event
occurs. If the CLDAT or FLTDAT bits are set to ‘1’,
and their associated event occurs, then these
asserted outputs will be delayed by clocked logic
in the dead-time circuitry.
12.29 Asserting Outputs via Current
Limit
It is possible to use the CLDAT bits to assert the
PWMxH,L outputs in response to a current-limit event.
Such behavior could be used as a current “force” fea-
ture in response to an external current or voltage mea-
surement that indicates a sudden sharp increase in the
load on the power-converter output. Forcing the PWM
“ON” could be viewed as a “Feed-Forward” term that
allows quick system response to unexpected load
increases without waiting for the digital control loop to
respond.
12.30 PWM Immediate Update
For high-performance PWM control-loop applications,
the user may want to force the duty cycle updates to
occur immediately. Setting the IUE bit in the
PWMCONx register enables this feature.
In a closed-loop control application, any delay between
the sensing of a system’s state and the subsequent
outputting of PWM control signals that drive the appli-
cation reduces the loop stability. Setting the IUE bit
minimizes the delay between writing the duty cycle reg-
isters and the response of the PWM generators to that
change.
12.31 PWM Output Override
All control bits associated with the PWM output
override function are contained in the IOCONx register.
If the PENH, PENL bits are set, the PWM module
controls the PWMx output pins.
The PWM output override bits allow the user to manu-
ally drive the PWM I/O pins to specified logic states
independent of the duty cycle comparison units.
The OVRDAT<1:0> bits in the IOCONx register deter-
mine the state of the PWM I/O pins when a particular
output is overridden via the OVRENH,L bits.
The OVRENH, OVRENL bits are active high control
bits. When the OVREN bits are set, the corresponding
OVRDAT bit overrides the PWM output from the PWM
generator.
12.31.1
COMPLEMENTARY OUTPUT MODE
When the PWM is in Complementary Output mode, the
dead-time generator is still active with overrides. The
output overrides and Fault overrides generate control
signals used by the dead-time unit to set the outputs as
requested, including dead time.
Dead-time insertion can be performed when PWM
channels are overridden manually.
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