- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄362053 > AC162834ADGG (NXP SEMICONDUCTORS) 18-bit registered driver with inverted register enable and 30ohm termination resistors 3-State PDF資料下載
參數(shù)資料
| 型號(hào)： | AC162834ADGG |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | 18-bit registered driver with inverted register enable and 30ohm termination resistors 3-State |
| 中文描述： | ALVC/VCX/A SERIES, 18-BIT DRIVER, TRUE OUTPUT, PDSO56 |
| 封裝： | 6.10 MM, PLASTIC, SOT-364-1, TSSOP2-56 |
| 文件頁(yè)數(shù)： | 2/12頁(yè) |
| 文件大?。?/td> | 122K |
| 代理商： | AC162834ADGG |
Philips Semiconductors
Product specification
74ALVC162834A
18-bit registered driver with inverted register enable
and 30
termination resistors (3-State)
2
2000 Mar 14
853–2193 23314
FEATURES
Wide supply voltage range of 1.2 V to 3.6 V
Complies with JEDEC standard no. 8-1A.
CMOS low power consumption
Direct interface with TTL levels
Current drive
±
12 mA at 3.0 V
MULTIBYTE
TM
flow-through standard pin-out architecture
Low inductance multiple V
CC
and GND pins for minimum noise
and ground bounce
Output drive capability 50
transmission lines @ 85
°
C
Integrated 30 termination resistors
Diode clamps to V
CC
and GND on all inputs
Input diodes to accommodate strong drivers
DESCRIPTION
The 74ALVC162834A is an 18-bit registered driver. Data flow is
controlled by active low output enable (OE), active low latch enable
(LE) and clock inputs (CP).
When LE is LOW, the A to Y data flow is transparent. When LE is
HIGH and CP is held at LOW or HIGH, the data is latched; on the
LOW to HIGH transient of CP the A-data is stored in the
latch/flip-flop.
The 74ALVC162834A is designed with 30 _series resistors in both
HIGH or LOW output stages.
When OE is LOW the outputs are active. When OE is HIGH, the
outputs go to the high impedance OFF-state. Operation of the OE
input does not affect the state of the latch/flip -flop.
To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pullup resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
NC
NC
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
GND
V
CC
GND
Y
7
Y
8
Y
9
Y
10
Y
11
Y
12
GND
Y
13
Y
14
Y
15
V
CC
Y
16
Y
17
GND
Y
18
OE
LE
GND
NC
A
1
GND
A
2
A
3
V
CC
A
4
A
5
A
6
GND
A
7
A
8
A
9
A
10
A
11
A
12
GND
A
13
A
14
A
15
V
CC
A
16
A
17
GND
A
18
CP
GND
SH00194
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
≤
2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
Propagation delay
An to Yn;
LE to Yn;
CP to Yn
V
CC
= 3.3 V, C
L
= 50 pF
2.9
3.5
3.3
ns
F
max
C
I
C
I/O
Maximum clock frequency
V
CC
= 3.3 V, C
L
= 50 pF
240
MHz
Input capacitance
4.0
pF
Input/Output capacitance
8.0
pF
C
PD
Power dissipation capacitance per buffer
V = GND to V
CC1
transparent mode
Output enabled
Output disabled
10
3
pF
Clocked mode
Output enabled
Output disabled
21
15
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
in
μ
W):
P
D
= C
PD
×
V
CC2
×
f
i
+ (C
L
×
V
CC2
×
f
o
) where: f
i
= input frequency in MHz; C
L
= output load capacitance in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V; (C
L
×
V
CC2
×
f
o
) = sum of outputs.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AC164010 | SOCKELMODUL |
| AC164012 | SOCKELMODUL |
| AC164026 | SOCKET MODULE SOIC/TSSOP |
| AC174002 | SOCKELMODUL |
| AC164001 | SOCKELMODUL |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AC-162A | 制造商:ZETTLER 制造商全稱:ZETTLER Electronics 功能描述:SPECIFICATIONS FOR LCD MODULE |
| AC-162B | 制造商:ZETTLER 制造商全稱:ZETTLER Electronics 功能描述:SPECIFICATIONS FOR LCD MODULE |
| AC-162C | 制造商:ZETTLER 制造商全稱:ZETTLER Electronics 功能描述:SPECIFICATIONS FOR LCD MODULE |
| AC-162D | 制造商:ZETTLER 制造商全稱:ZETTLER Electronics 功能描述:SPECIFICATIONS FOR LCD MODULE |
| AC-162DGA | 制造商:ZETTLER 制造商全稱:ZETTLER Electronics 功能描述:SPECIFICATIONS FOR LCD MODULE |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。