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參數(shù)資料
| 型號： | ABT22V10A7A |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | PLD |
| 英文描述： | GT 6C 3#0 3#12 SKT PLUG RTANG |
| 中文描述： | OT PLD, 8 ns, PQCC28 |
| 文件頁數(shù)： | 5/18頁 |
| 文件大?。?/td> | 302K |
| 代理商： | ABT22V10A7A |
Philips Semiconductors
Product specification
ABT22V10A5, A7
5V high-speed universal PLD device
with live insertion capability
1996 Dec 16
5
AC ELECTRICAL CHARACTERISTICS
1
4.75V
≤
V
CC
≤
5.25V; 0 C
≤
T
amb
≤
+75 C
SYMBOL
PARAMETER
TEST
CONDITIONS
LIMITS
UNIT
ABT22V10A5
ABT22V10A7
MIN
TYP
MAX
MIN
TYP
MAX
t
PD
non-registered output
2
Active-LOW
2.0
4.5
5.0
2.0
6.0
7.5
ns
Input or feedback to
Active-HIGH
2.0
4.5
5.0
2.0
6.0
7.5
ns
t
S
Setup time from input or SP
to Clock
2.0
1.3
3.5
3.0
ns
t
SIO
Setup time from feedback
to Clock
2.25
1.5
3.5
3.0
ns
t
H
Hold time
0
0
ns
t
SKEWR
Skew between registered
outputs
4, 7
1.0
1.0
ns
t
CO
Clock to output
2.0
3.5
4.0
2.0
4.5
5.5
ns
t
CF
Clock to feedback
3
2.0
4.0
3.0
5.0
ns
t
AR
Asynchronous Reset to
registered output
10.0
10.0
ns
t
ARW
Asynchronous Reset width
6.0
7.5
ns
t
ARR
Asynchronous Reset
recovery time
4.0
5.5
ns
t
SPR
Synchronous Preset
recovery time
4.5
5.0
ns
t
WL
Width of Clock LOW
2.0
3.0
ns
t
WH
Width of Clock HIGH
2.0
3.0
ns
f
MAX
Maximum frequency;
External feedback
1/(t
S
+ t
CO
)
4
167
208
111
133
MHz
Maximum frequency;
Internal feedback
1/(t
S
+ t
CF
)
4
167
303
125
166
MHz
t
EA
Input to Output Enable
5
8.0
8.0
ns
t
ER
Capacitance
6
Input to Output Disable
5
7.5
7.5
ns
C
IN
Input Capacitance (Pin 2)
V
IN
= 2.0V
8
8
pF
Input Capacitance (Others)
V
IN
= 2.0V
V
CC
= 5.0V
T
amb
= 25
°
C
4
4
pF
C
OUT
Output Capacitance
V
OUT
= 2.0V
8
8
pF
NOTES:
1. Test Conditions: R
1
= 300
, R
2
=390
2. t
PD
is tested with switch S
1
closed and C
L
= 50pF (including jig capacitance). V
IH
= 3V, V
IL
= 0V, V
T
= 1.5V.
3. Calculated from measured f
MAX
internal.
4. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency
may be affected.
5. For 3-State output; output enable times are tested with C
= 50pF to the 1.5V level, and S
is open for high-impedance to High tests and
closed for high-impedance to Low tests. Output disable times are tested with C
5pF. High-to-High impedance tests are made to an output
voltage of V
T
= (V
OH
– 0.5V) with S
1
open, and Low-to-High impedance tests are made to the V
T
= (V
OL
+ 0.5V) level with S
1
closed.
6. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where
capacitance may be affected.
7. Skew is measured with all outputs switching in the same direction.
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