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參數(shù)資料
| 型號： | ABT22V10A7 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 5V high-speed universal PLD device with live insertion capability(具有活插入能力的5V高速通用PLD器件) |
| 中文描述： | 5V的高速插入活通用PLD器件的能力（具有活插入能力的5V的高速通用可編程邏輯器件） |
| 文件頁數(shù)： | 10/18頁 |
| 文件大?。?/td> | 302K |
| 代理商： | ABT22V10A7 |
Philips Semiconductors
Product specification
ABT22V10A5, A7
5V high-speed universal PLD device
with live insertion capability
1996 Dec 16
10
OUTPUT MACRO CELL
F
0
1
1
0
0
1
0
0
1
CLK
1
AR
SP
S
1
S
0
S
1
S
0
OUTPUT CONFIGURATION
0 = Unprogrammed fuse
1 = Programmed fuse
D
Q
Q
0
0
1
1
0
1
0
1
Registered/Active-LOW
Registered/Active-HIGH
Combinatorial/Active-LOW
Combinatorial/Active-HIGH
SP00375
Figure 2. Output Macro Cell Logic Diagram
F
CLK
AR
SP
S
0
= 0
S
1
= 0
D
Q
Q
a. Registered/Active-LOW
F
CLK
AR
SP
S
0
= 1
S
1
= 0
D
Q
Q
b. Registered/Active-HIGH
F
S
0
= 0
S
1
= 1
c. Combinatorial/Active-LOW
d. Combinatorial/Active-HIGH
F
S
0
= 1
S
1
= 1
SP00376
Figure 3. Output Macro Cell Configurations
Registered Output Configuration
Each Macro Cell of the ABT22V10A includes a D-type flip-flop for
data storage and synchronization. The flip-flop is loaded on the
LOW-to-HIGH transition of the clock input. In the registered
configuration (S
1
= 0), the array feedback is from Q of the flip-flop.
Combinatorial I/O Configuration
Any Macro Cell can be configured as combinatorial by selecting the
multiplexer path that bypasses the flip-flop (S
1
= 1). In the
combinatorial configuration, the feedback is from the pin.
Variable Input/Output Pin Ratio
The ABT22V10A has twelve dedicated input lines, and each Macro
Cell output can be an I/O pin. Buffers for device inputs have
complementary outputs to provide user-programmable input signal
polarity.
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