參數(shù)資料
型號: AAT3236IJS-2.9-T1
廠商: Advanced Analog Technology,lnc.
英文描述: 300mA CMOS High Performance LDO
中文描述: 300mA的LDO穩(wěn)壓器的CMOS高性能
文件頁數(shù): 14/18頁
文件大?。?/td> 220K
代理商: AAT3236IJS-2.9-T1
AAT3236
300mA CMOS High Performance LDO
14
3236.2007.03.1.4
Figure 1: Common LDO Regulator Layout with C
BYP
Ripple Feedback Loop.
Figure 2: Recommended LDO Regulator Layout.
LDO
Regulator
C
BYP
C
OUT
R
TRACE
R
TRACE
R
TRACE
R
TRACE
C
IN
R
LOAD
V
IN
EN
GND
V
OUT
BYP
V
IN
GND
I
IN
I
LOAD
I
GND
I
RIPPLE
DC INPUT
I
LOAD
return + noise and ripple
I
BYP
only
LDO
Regulator
C
BYP
C
OUT
R
TRACE
R
TRACE
R
TRACE
R
TRACE
C
IN
R
LOAD
V
IN
EN
GND
V
OUT
BYP
I
LOAD
I
RIPPLE
I
IN
V
IN
GND
DC INPUT
I
GND
C
BYP
LOOP
I
LOAD
return + noise and ripple
I
BYP
+ noise
tion to ground and the LDO regulator ground con-
nection. When the high load current returns through
this path, a small ripple voltage is created, feeding
into the C
BYP
loop.
Figure 2 shows the preferred method for the
bypass and output capacitor connections. For low
output noise and highest possible power supply
ripple rejection performance, it is critical to connect
the bypass and output capacitor directly to the LDO
regulator ground pin. This method will eliminate
any load noise or ripple current feedback through
the LDO regulator.
Evaluation Board Layout
The AAT3236 evaluation layout (Figures 3, 4, and
5) follows the recommend printed circuit board lay-
out procedures and can be used as an example for
good application layouts.
Note: Board layout shown is not to scale.
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