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參數(shù)資料
| 型號： | AAT1230-1 |
| 廠商： | Advanced Analog Technology,lnc. |
| 英文描述： | 18V 100mA Step-Up Converter |
| 中文描述： | 18V的100mA的升壓轉(zhuǎn)換器 |
| 文件頁數(shù)： | 14/21頁 |
| 文件大?。?/td> | 511K |
| 代理商： | AAT1230-1 |
AAT1230/1230-1
18V 100mA Step-Up Converter
14
1230.2006.10.1.4
Option 3: Dynamic Voltage Control Using
S
2
Cwire Interface
The output can be dynamically adjusted by the host
controller to any of 16 pre-set output voltage levels
using the integrated S
2
Cwire interface. The
EN/SET pin serves as the S
2
Cwire interface input.
The SEL pin must be pulled low when using the
S
2
Cwire interface.
S
2
Cwire Serial Interface
AnalogicTech's S
2
Cwire serial interface is a propri-
etary high-speed single-wire interface available
only from AnalogicTech. The S
2
Cwire interface
records rising edges of the EN/SET input and
decodes into 16 different states. Each state corre-
sponds to a voltage setting on the FB2 pin, as
shown in Table 2.
S
2
Cwire Serial Interface Timing
The S
2
Cwire serial interface has flexible timing.
Data can be clocked-in at speeds up to 1MHz. After
data has been submitted, EN/SET is held high to
latch the data for a period T
LAT
. The output is sub-
sequently changed to the predetermined voltage.
When EN/SET is set low for a time greater than
T
OFF
, the AAT1230/1230-1 is disabled. When dis-
abled, the register is reset to the default value, which
sets the FB2 pin to 0.6V if EN is subsequently pulled
high.
S
2
Cwire Output Voltage Programming
The AAT1230/1230-1 is programmed through the
S
2
Cwire interface according to Table 2. The rising
clock edges received through the EN/SET pin
determine the feedback reference and output volt-
age set-point. Upon power up with the SEL pin
low and prior to S
2
Cwire programming, the default
feedback reference voltage is set to 0.6V.
Table 2: S
2
Cwire Voltage Control Settings
(SEL = Low).
EN/SET
Rising
Edges
FB2
EN/SET
Rising
Edges
FB2
Reference
Voltage (V)
Reference
Voltage (V)
1
2
3
4
5
6
7
8
0.60 (Default)
0.64
0.68
0.72
0.76
0.80
0.84
0.88
9
10
11
12
13
14
15
16
0.92
0.96
1.00
1.04
1.08
1.12
1.16
1.20
Figure 2: S
2
Cwire Timing Diagram to Program the Output Voltage.
1
EN/SET
2
n-1
n
≤
16
Data Reg
0
n-1
0
T
HI
T
LO
T
LAT
T
OFF
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