參數(shù)資料
型號(hào): A8450
廠商: Allegro MicroSystems, Inc.
英文描述: Automotive Multioutput Voltage Regulator
中文描述: 汽車Multioutput穩(wěn)壓器
文件頁數(shù): 8/15頁
文件大小: 549K
代理商: A8450
8
A8450KLB-DS, Rev. 1
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
115 Northeast Cutoff, Box 15036
Allegro MicroSystems, Inc.
A8450
Automotive Multioutput Voltage Regulator
short is applied to the regulator output, either V5A or V5D,
the current folds back to 0 V at 50 mA, as shown in figure 4a.
The voltage recovers to its regulated output when the short is
removed.
The V5A and V5D regulators track each other during power-
on, and when the device is enabled and ramped up out of
disabled mode, the regulators will start to track when V
REG
reaches approximately 1.8 V. These regulators are guaranteed
to track to within 0.5% of each other under normal operating
conditions.
3.3 V and Adjustable Linear Regulators
.
Two additional
linear regulators, one that outputs at 3.3 V, and another that has
a 1.2 V to 3.3 V adjustable output, can be implemented using
external npn pass transistors. The output voltage of the adjust-
able regulator, V
OUTVADJ
(V), is set by the values of the output
resistors, R1 and R2 (
). It can be calculated as
V
OUTVADJ
=
V
FB
(1+R1
R2)
where V
FB
(V) is the voltage on the feedback pin, FB.
Additional pins, CL33 and CLADJ, are provided for setting
current limits. These are used to protect the external pass transis-
tors from a short-to-ground condition. The current limit setting,
I
CL
(mA), is calculated using the formula
I
CL
=
V
OC
R
RCL
where RCL (
) is the current-limiting resistor corresponding to
that regulator (R3 for the 3.3 V regulator, and R4 for the adjust-
able regulator). When I
CL
is exceeded, the maximum load current
through that regulator is folded back to 40% of I
CL
±10%, as
shown in figure 4b. If current limiting is not needed, the CL33
and CLADJ pins should be shorted to the VREG pin.
Disabled Mode
.
When the two input signal pins, ENBAT
and ENB, are pulled low, the A8450 enters disabled mode.
This is a sleep mode, in which all internal circuitry is dis-
abled in order to draw a minimal current from VBB. When
either of these pins is pulled high, the device is enabled.
When emerging from disabled mode, the buck converter
switching regulator does not operate until the charge pump
has stabilized (
300 μs).
Enabled Mode
. When one or both of the signal input
pins, ENBAT and ENB, are in the high state, the A8450 is
enabled.
6
0
50
100
150
200
250
300
1600
5
4
3
2
1
0
5V Regulators Overcurrent Foldback
I
OUT
(mA)
V
O
(
I
OUTV5DLIM
and I
OUTV5ALIM
Figure 4a. Linear foldback to 50 mA. Foldback occurs at the
typical current limit for the 5 V regulator.
Figure 4b. Linear foldback to a percentage of I
CL
. Foldback
occurs at the current limit setting for the regulator.
6
0
I
CL
1600
5
4
3
2
1
0
3.3 V and Adjustable Regulators Overcurrent Foldback
I
OUT
(mA)
V
O
(
0.4
I
CL
±10%
V
OUTVADJ(min)
V
OUTV33
and V
OUTVADJ(max)
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