參數(shù)資料
型號(hào): A8450
廠商: Allegro MicroSystems, Inc.
英文描述: Automotive Multioutput Voltage Regulator
中文描述: 汽車(chē)Multioutput穩(wěn)壓器
文件頁(yè)數(shù): 13/15頁(yè)
文件大?。?/td> 549K
代理商: A8450
13
A8450KLB-DS, Rev. 1
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
115 Northeast Cutoff, Box 15036
Allegro MicroSystems, Inc.
A8450
Automotive Multioutput Voltage Regulator
A8450 Power Dissipation
. The A8450 is designed to
operate in applications with high ambient temperatures. The
total power dissipated in the device must be considered in
conjunction with the thermal dissipation capabilities of the
PCB where the A8450 is mounted, as well as the capabilities
of the device package itself.
The ability of a package to dissipate heat is approximated by
the thermal resistance from the die (junction) to the ambi-
ent environment, R
θ
JA
(°C/W). This includes the significant
effect of dissipation through the package leads and the PCB
on which the package is mounted, and the temperature of the
ambient air. Test results for this 24-lead SOIC are approxi-
mately 35 °C/W when mounted on a high-thermally conduc-
tive PCB (based on the JEDEC standard PCB, having four
layers with buried copper areas).
The total power that can be applied to the device, P
D(lim)
(W),
is affected by the maximum allowable device junction
temperature, T
J(max)
(°C), R
θ
JA
, and the ambient air tempera-
ture, T
A
(°C), as shown in the following formula
P
D(lim)
= (T
J(max)
– T
A
)
R
θ
JA
P
D(lim)
can be estimated based on several parameters, using
the following formula
P
D(lim)
= P
D(Ibias)
+ P
D(V5A)
+ P
D(V5D)
+ P
D(buckdc)
+ P
D(buckac)
+ P
D(BD)
where
P
D(Ibias)
= V
BB
×
I
BB
P
D(V5A)
= (V
REG
– 5 V)
×
I
LOAD(V5A)
P
D(V5D)
= (V
REG
– 5 V)
×
I
LOAD(V5D)
P
D(buckdc)
= I
LOAD2
×
R
DSON(TJmax)
×
DC
P
D(buckac)
= I
LOAD
×
[V
BB
( 5 ns
14 V)
×
V
BB
]
×
0.5 f
PWM
P
D(BD)
= I
V33BD(max)
×
(V
REG
– 4 V) + I
VADJBD(max)
×
(V
REG
– V
ADJ
– 0.7 V)
and
I
LOAD
= I
LOAD(V33)
+ I
LOAD(VADJ)
+ I
LOAD(V5D)
+ I
LOAD(V5A)
R
DSON
is a function of T
J
. For the purposes of estimating
P
D(lim)
, the relationship can be assumed to be linear through-
out the practical T
J
operating range (see test conditions for
R
DSON
in the Electrical Characteristics table).
DC (duty cycle) is a function of V
BB
and V
REG
. This can be
calculated precisely as
DC = V
REG(off)
(V
REG(on)
+ V
REG(off)
)
A rough estimate for DC is
DC = (V
REG
+ V
LX
)
V
BB
I
V33BD(max)
is the maximum current drawn on the V33BD
pin. It is dependent on I
OUTV33
and the h
FE
of the pass tran-
sistor.
I
ADJBD(max)
is the maximum current drawn on the VADJBD
pin. It is dependent on I
OUTVADJ
and the h
FE
of the pass
transistor.
Overcurrent Protection
The current supplied by the 3.3 V and the 1.2 to 3.3 V adjust-
able regulators is limited to
I
CL
. Current above
I
CL
is folded
back linearly, as shown in figure 4b. In the case of a shorted
load, the collector current is reduced to 40% of
I
CL
±10% ,
to ensure protection of the pass transistors. After the short is
removed, the voltage recovers to its regulated level.
The maximum power dissipated in the transistor during a
shorted load condition is:
P
D
(
V
REG
V
OUT
)
×
(0.4
×
I
CL
)
where V
OUT
= 0 V.
Low Input Voltage Operation
When the charge pump has ramped enough to enhance
the buck switch, the buck converter switching regulator is
enabled. This occurs at V
BB
5.7 V. At that point, the duty
cycle, DC, of the A8450 can be forced to 100% until V
IN
is
high enough to allow the switch to begin operating normally.
The point at which normal switching begins is dependent
on ambient temperature, T
A
. Increases in T
A
cause R
DSON
to
increase. Other significant factors are I
LOAD
, V
REG
, the ESR
of the output inductor (L1), and the forward biasing voltage
for the output Schottky diode (D1).
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