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| 型號(hào)： | A8423KL |
| 廠商： | Allegro MicroSystems, Inc. |
| 英文描述： | LIN Bus Transceiver with Integrated Voltage Regulator |
| 中文描述： | LIN總線收發(fā)器集成穩(wěn)壓器 |
| 文件頁(yè)數(shù)： | 2/8頁(yè) |
| 文件大?。?/td> | 368K |
| 代理商： | A8423KL |
2
Worcester, Massachusetts 01615-0036 (508) 853-5000
115 Northeast Cutoff, Box 15036
www.allegromicro.com
D
A
A8423
LIN Bus Transceiver with Integrated Voltage Regulator
Preliminary – Subject to Change
Without Notice February 9, 2004
ELECTRICAL CHARACTERISTICS
at T
J
= –40°C to 150oC, V
SUP
= 7 V to 18 V (unless otherwise noted)
Characteristics
VSUP Power Supply
Operating Voltage Range
Symbol
Test Conditions
Min.
Typ.
Max.
Units
V
SUP
V
SUP
Continuous
Transient; 500 ms
LIN output recessive (High); V
WAKE
= 0
LIN output dominant (Low); V
= 0
V
WAKE
= 0, LIN = N.C.
LIN = Dominant (Low), Wake = N.C.
IREG < 20 μA
7
–
–
–
–
–
–
–
–
30
40
1
2
1
2
100
5.2
V
V
Supply Current
I
SUP
0.8
1.5
0.8
1.5
80
5.0
mA
mA
mA
mA
μA
V
Supply Standby Current
I
STBY
Supply Sleep Current
Undervoltage Threshold
TX and EN Input
Low Level Input Voltage
High Level Input Voltage
Input Hysteresis
Pull-Down Resistor
Pull-Up Resistor
RX Output
Low Level Output Current
High Level Leakage Current
Wake Input
Low Level Input Voltage
High Level Input Voltage
Pull-up Current
High Level Leakage Current
VREG Regulated 5V Supply
Output Voltage
Output Current Limit
External Decoupling Cap
Line Regulation
Load Regulation
LIN Interface
Output Short Circuit Current
Output Voltage – Recessive
Output Voltage – Dominant
High Level Leakage Current
Termination Resistance
Input Threshold – Dominant
Input Threshold – Recessive
Input Threshold Hysteresis
I
SLEEP
VSUP
UV
4.8
V
IL
V
IH
V
IHYS
R
PD
R
PU
–
2
–
60
60
–
–
0.8
–
–
200
200
V
V
300
100
100
mV
k
k
EN pin
TX pin
I
OL
I
OH
V
RX
= 0.4 V
V
RX
= 5 V
1.5
–
–
–
–
5
mA
μA
V
IL
V
IH
I
IL
I
IH
–
–
–
V
SUP
–5
–
–
5
V
V
μA
μA
V
SUP
–1
–
–
V
WAKE
= 0 V
V
WAKE
= V
SUP
= 30 V
40
–
V
REG
IREG
LIM
I
OUT
= 0 to 50 mA
V
REG
= 0 V
V
REG
to GND
I
OUT
= 30 mA
V
SUP
= 13.5 V; I
OUT
= 1 to 30 mA
4.5
–
1
–
–
5.0
–
–
–
–
5.5
180
–
100
100
V
mA
μF
mV
mV
I
OSC
V
OR
V
OD
I
IH
R
SLAVE
V
THDOM
V
THREC
VLIN
HYS
60
85
–
1
–
30
–
–
110
–
1.2
10
47
–
mA
V
V
μA
k
V
V
V
V
TX
= 5 V; I
LIN
= 0 mA
V
TX
= 0 V; I
LIN
= 40 mA
V
LIN
= V
SUP
0.9 V
SUP
–
–
20
0.4 V
SUP
–
0.05 V
SUP
V
LIN
– Recessive to Dominant
V
LIN
– Dominant to Recessive
0.6 V
SUP
0.1 V
SUP
0.175 V
SUP
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