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參數(shù)資料
| 型號(hào)： | A82DL32X4T |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL32x4T(U) 32 Megabit (4Mx8 Bit/2Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash |
| 中文描述： | 堆疊式多芯片封裝（MCP）閃存和SRAM，A82DL32x4T（ü）32兆位（4Mx8 Bit/2Mx16位）的CMOS 3.3伏只，同時(shí)閃電行動(dòng) |
| 文件頁數(shù)： | 9/60頁 |
| 文件大?。?/td> | 931K |
| 代理商： | A82DL32X4T |
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A82DL32x4T(U) Series
PRELIMINARY
(August, 2005, Version 0.0)
8
AMIC Technology, Corp.
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register itself does
not occupy any addressable memory location. The register is
composed of latches that store the commands, along with
the address and data information needed to execute the
command. The contents of the register serve as inputs to the
internal state machine. The state machine outputs dictate the
function of the device. The appropriate device bus operations
table lists the inputs and control levels required, and the
resulting output. The following subsections describe each of
these operations in further detail.
Table 1-1. Device Bus Operations – Flash Byte Mode (
BYTE_F
= V
IH
)
Operation
(Notes 1, 2)
CE_F
E1_S
C
CE2_S
OE
WE
A0-
A20
LB_S
(Note3)
UB_S
(Note3)
RESET
WP
/ACC
(Note 4)
I/O
7
–
I/O
0
I/O
15
–
I/O
0
H
X
Read from Flash
L
X
L
L
H
A
IN
X
X
H
L/H
I
OUT
I
OUT
H
X
Write to Flash
L
X
L
H
L
A
IN
X
X
H
(Note 4)
I
IN
I
IN
H
X
Standby
VCC ±
0.3 V
X
L
X
X
X
X
X
VCC ±
0.3 V
H
High-Z
High-Z
L
X
Output Disable
L
L
H
H
H
X
X
L
H
L/H
High-Z
High-Z
H
X
X
L
Flash Hardware
Reset
X
H
X
X
X
X
X
X
L
L/H
High-Z
High-Z
X
L
Sector Protect
(Notes)
L
H
X
H
L
SA,
A6 = L,
A1 = H,
A0 = L
X
X
V
ID
L/H
I
IN
X
Sector Unprotect
(Note 5)
L
X
L
H
L
SA,
A6 = H,
A1 = H,
A0 = L
X
X
V
ID
(Note 6)
I
IN
X
H
X
I
IN
High-Z
Temporary
Sector Unprotect
X
X
L
X
X
A
IN
X
X
V
ID
(Note 6)
I
OUT
I
OUT
H
L
High-Z
I
OUT
L
H
I
OUT
High-Z
Read from
SRAM
H
L
H
L
H
A
IN
L
L
H
X
I
IN
I
IN
H
L
High-Z
I
IN
Write to SRAM
H
L
H
X
L
A
IN
L
H
H
X
I
IN
High-Z
Legend: L = Logic Low = V
IL
, H = Logic High = V
IH
, V
ID
= 8.5–12.5 V, V
HH
= 9.0 ± 0.5 V, X = Don’t Care, SA = Sector Address,
A
IN
= Address In, I
IN
= Data In, I
OUT
= Data Out
Notes:
1.Other operations except for those indicated in this column are inhibited.
2.Do not apply
CE_F
= V
IL
,
CE1_S
= V
IL
and CE2_S = V
IH
at the same time.
3.Don’t care or open
LB_S
or
UB_S
.
4.The sector protect and sector unprotect functions may also be implemented via programming equipment. See the
“Sector/Sector Block Protection and Unprotection” section.
5. If
WP
/ACC = V
IL
, the two outermost boot sectors remain protected. If
WP
/ACC = V
IH
, the two outermost boot sector
protection depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block
Protection and Unprotection”. If
WP
/ACC = V
HH
, all sectors will be unprotected.
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