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參數(shù)資料
| 型號： | A82DL32X4T |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL32x4T(U) 32 Megabit (4Mx8 Bit/2Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash |
| 中文描述： | 堆疊式多芯片封裝（MCP）閃存和SRAM，A82DL32x4T（ü）32兆位（4Mx8 Bit/2Mx16位）的CMOS 3.3伏只，同時閃電行動 |
| 文件頁數(shù)： | 34/60頁 |
| 文件大?。?/td> | 931K |
| 代理商： | A82DL32X4T |
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A82DL32x4T(U) Series
PRELIMINARY
(August, 2005, Version 0.0)
33
AMIC Technology, Corp.
Table 13. Write Operation Status
I/O
7
I/O
6
I/O
5
I/O
3
I/O
2
RY/
BY
Status
(Note 2)
(Note 1)
(Note 2)
Embedded Program Algorithm
7
I/O
0
Toggle
0
N/A
No toggle
0
Standard
Mode
Embedded Erase Algorithm
Toggle
0
1
Toggle
0
Erase
Suspended Sector
Non-Erase
Suspend Sector
1
No toggle
0
N/A
Toggle
1
Erase-Suspend-
Read
Data
Data
Data
Data
Data
1
Erase
Suspend
Mode
Erase-Suspend-Program
7
I/O
Toggle
0
N/A
N/A
0
Notes:
1. I/O
5
switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
Refer to the section on I/O
5
for more information.
2. I/O
7
and I/O
2
require a valid address when reading status information. Refer to the appropriate subsection for further details.
3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm
is in progress. The device outputs array data if the system addresses a non-busy bank.
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