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參數(shù)資料
| 型號(hào)： | A8287SLB |
| 廠商： | Allegro MicroSystems, Inc. |
| 英文描述： | LNB Supply and Control Voltage Regulator |
| 中文描述： | LNB電源和控制穩(wěn)壓器 |
| 文件頁(yè)數(shù)： | 9/17頁(yè) |
| 文件大?。?/td> | 527K |
| 代理商： | A8287SLB |
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9
Worcester, Massachusetts 01615-0036 (508) 853-5000
115 Northeast Cutoff, Box 15036
www.allegromicro.com
D
P
2
A8285/A8287
LNB Supply and Control Voltage Regulator
SDA line before the ninth clock cycle, in order to allow this
handshaking to occur.
During a data read, the A8285/A8287 acknowledges the
address in the same way as in the data write sequence, and
hen retains control of the SDA line and send the data to the
master. On completion of the eight data bits, the A8285/
A8287 releases the SDA line before the ninth clock cycle,
in order to allow the master to acknowledge the data. If the
master holds the SDA line low during this Acknowledge bit,
the A8285/A8287 responds by sending another data byte to
the master. Data bytes continue to be sent to the master until
the master releases the SDA line during the Acknowledge bit.
When this is detected, the A8285/A8287 stops sending data
and waits for a stop signal.
Interrupt Request
.
The A8285/A8287 also provides an
interrupt request pin IRQ, which is an open-drain, active-
low output. This output may be connected to a common
IRQ line with a suitable external pull-up and can be used
with other I
2
C devices to request attention from the master
controller. The IRQ output becomes active when either the
A8285/A8287
fi
rst recognizes a fault condition, or at power-
on when the main supply V
and the internal logic supply
V
reach the correct operating conditions. It is only reset
to inactive when the I
2
C master addresses the A8285/A8287
with the Read/Write bit set (causing a read). Fault conditions
are indicated by the TSD, VUV, and OCP bits in the status
register (see description of OCP for conditions of use). The
DIS and PNG bits do not cause an interrupt. When the mas-
ter recognizes an interrupt, it addresses all slaves connected
to the interrupt line in sequence, and then reads the status
register to determine which device is requesting attention.
The A8285/A8287 latches all conditions in the status regis-
ter until the completion of the data read.
The action at the resampling point is further de
fi
ned in the
description for each of the status bits. The bits in the status
register are de
fi
ned such that the all-zero condition indicates
that the A8285/A8287 is fully active with no fault conditions.
When V
IN
is initially applied, the I
2
C interface does not
respond to any requests until the internal logic supply V
has reached its operating level. Once V
REG
has reached this
point, the IRQ output goes active, and the VUV bit is set.
After the A8285/A8287 acknowledges the address, the IRQ
fl
ag is reset. Once the master reads the status registers, the
registers are updated with the VUV reset.
Control Register (I
2
C Write Register).
All main func-
tions of the A8285/A8287 are controlled through the I
2
C
interface via the 8-bit Control register. This register allows
selection of the output voltage and current limit, enabling and
disabling the LNB output, and switching the 22 kHz tone on
and off. The power-up state is 0 for all of the control functions.
Bit 0 (VSEL0), Bit 1 (VSEL1), and Bit 2 (VSEL2)
. These
provide incremental control over the voltage on the LNB
output. The available voltages provide the necessary levels
for all the common standards plus the ability to add line
compensation in increments of 333 mV The voltage levels
are de
fi
ned in the Output Voltage Amplitude Selection table.
Bit 3 (VSEL3)
. Switches between the low-level and high-
level output voltages on the LNB output. A value of 0 selects
the low level voltage and a value of 1 selects the high level.
The low-level center voltage is 12.709 V nominal, and the
high level is 18.042 V nominal. These may be increased, in
increments of 333 mV by using the VSEL2, VSEL1, and
VSEL0 control register bits.
Bit 4 (ODT)
. When set to 1, enables the ODT feature
(disables the A8285/A8287 if the overcurrent disable time
is exceeded during an overcurrent condition on the output).
When set to 0, the ODT feature is disabled.
0
0
0
1
0
A1 A0
1
AK
D6 D5 D4 D3 D2 D1 D0
D7
NAK
Status Data
Address
Start
R
Stop
1
2
3
4
5
6
7
8
9
SDA
SCL
IRQ
Fault
Event
Reload
Status Register
Reading the Register After an Interrupt
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A8287SLB-T | 制造商:Allegro MicroSystems LLC 功能描述: |
| A8287SLBTR | 功能描述:IC REG LNB SUPPLY/CTRL 24-SOIC RoHS:否 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - 專用型 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,000 系列:- 應(yīng)用:電源，ICERA E400，E450 輸入電壓:4.1 V ~ 5.5 V 輸出數(shù):10 輸出電壓:可編程 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:42-WFBGA，WLCSP 供應(yīng)商設(shè)備封裝:42-WLP 包裝:帶卷 (TR) |
| A8287SLBTR-T | 功能描述:IC LNB SUPPLY/VOLTAGE REG 24SOIC RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - 專用型 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 應(yīng)用:控制器，DSP 輸入電壓:4.5 V ~ 25 V 輸出數(shù):2 輸出電壓:最低可調(diào)至 1.2V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:30-TFSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:30-TSSOP 包裝:帶卷 (TR) |
| A8290 | 制造商:ALLEGRO 制造商全稱:Allegro MicroSystems 功能描述:Single LNB Supply and Control Voltage Regulator |
| A8290SETTR-T | 功能描述:IC VOLTAGE REG SGL LNB 28-QFN RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - 專用型 系列:- 標(biāo)準(zhǔn)包裝:43 系列:- 應(yīng)用:控制器，Intel VR11 輸入電壓:5 V ~ 12 V 輸出數(shù):1 輸出電壓:0.5 V ~ 1.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-QFN（7x7） 包裝:管件 |
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