參數(shù)資料
型號(hào): A8287SLB
廠商: Allegro MicroSystems, Inc.
英文描述: LNB Supply and Control Voltage Regulator
中文描述: LNB電源和控制穩(wěn)壓器
文件頁(yè)數(shù): 8/17頁(yè)
文件大?。?/td> 527K
代理商: A8287SLB
8
Worcester, Massachusetts 01615-0036 (508) 853-5000
115 Northeast Cutoff, Box 15036
www.allegromicro.com
D
P
2
A8285/A8287
LNB Supply and Control Voltage Regulator
Timing Considerations
The control sequence of the communication through the I
2
C
interface is composed of several steps in sequence:
1.
Start Condition
. De
fi
ned by a negative edge on the SDA
line, while SCL is high.
2.
Address Cycle
. 7 bits of address, plus 1 bit to indicate
read (1) or write (0), and an acknowledge bit. The
fi
rst
fi
ve bits of the address are
fi
xed as:
00010
. The four
optional addresses, de
fi
ned by the remaining two bits, are
selected by the ADD input. The address is transmitted
MSB
fi
rst.
3.
Data Cycles
. 8 bits of data followed by an acknowledge
bit. Multiple data bytes can be read. Data is transmitted
MSB
fi
rst.
4.
Stop Condition
. De
fi
ned by a positive edge on the SDA
line, while SCL is high.
Except to indicate a Start or Stop condition, SDA must be
stable while the clock is high. SDA can only be changed
while SCL is low. It is possible for the Start or Stop condition
to occur at any time during a data transfer. The A8285/A8287
always responds by resetting the data transfer sequence.
The Read/Write bit is used to determine the data transfer
direction. If the Read/Write bit is high, the master reads one
or more bytes from the A8285/A8287. If the Read/Write bit
is low, the master writes one byte to the A8285/A8287. Note
that multiple writes are not permitted. All write operations
must be preceded with the address.
The Acknowledge bit has two functions. It is used by the
master to determine if the slave device is responding to its
address and data, and it is used by the slave when the master
is reading data back from the slave. When the A8285/A8287
decodes the 7-bit address
fi
eld as a valid address, it responds
by pulling SDA low during the ninth clock cycle.
During a data write from the master, the A8285/A8287 also
pulls SDA low during the clock cycle that follows the data
byte, in order to indicate that the data has been successfully
received. In both cases, the master device must release the
1
2
3
4
5
6
7
8
9
0
0
0
1
0
A1 A0
0
AK
AK
D6 D5
D4 D3
D2 D1 D0
D7
Control Data
Address
Start
W
Stop
SDA
SCL
acknowledge
from LNBR
acknowledge
from LNBR
0
0
0
1
0
A1 A0
1
AK
D6 D5 D4 D3 D2 D1 D0
D7
NAK
Status Data
Address
Start
R
Stop
1
2
3
4
5
6
7
8
9
SDA
SCL
no acknowledge
from master
acknowledge
from LNBR
0
0
0
1
0
A1 A0
1
AK
D6 D5 D4 D3
D2 D1
D0
D7
D6 D5 D4 D3 D2 D1 D0
D7
AK
NAK
Status Data
Address
Start
R
Stop
Status Data
1
2
3
4
5
6
7
8
9
SDA
SCL
acknowledge
from master
acknowledge
from LNBR
no acknowledge
from master
Writing to the Register
Reading One Byte from the Register
Reading Multiple Bytes from the Register
Application Information
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