- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375157 > A8287 (Allegro MicroSystems, Inc.) LNB Supply and Control Voltage Regulator PDF資料下載
參數(shù)資料
| 型號： | A8287 |
| 廠商： | Allegro MicroSystems, Inc. |
| 英文描述： | LNB Supply and Control Voltage Regulator |
| 中文描述： | LNB電源和控制穩(wěn)壓器 |
| 文件頁數(shù)： | 10/17頁 |
| 文件大小： | 527K |
| 代理商： | A8287 |
10
Worcester, Massachusetts 01615-0036 (508) 853-5000
115 Northeast Cutoff, Box 15036
www.allegromicro.com
D
P
2
A8285/A8287
LNB Supply and Control Voltage Regulator
Bit
Name
Function
0
VSEL0
See Output Voltage Amplitude
Selection Table
1
VSEL1
2
VSEL2
3
VSEL3
0: LNBx = Low range
1: LNBx = High range
4
ODT
0: Overcurrent disable time off
1: Overcurrent disable time on
5
ENB
0: Disable LNB Output
1: Enable LNB Output
6
ILIM
0: Overcurrent Limit = 500mA
1: Overcurrent Limit = 700mA
7
ENT
0: Disable Tone
1: Enable 22KHz internal tone
Bit 5 (ENB)
. When set to 1, enables the LNB output. When
set to 0, the LNB output is disabled.
Bit 6 (I
LIM
)
. Selects the I
LIM
level. When set to 0, the lower
limit (typically 500 mA) is selected. When set to 1, the
higher limit (typically 700 mA), is selected.
Bit 7 (ENT)
. When set to 1, enables modulation of the
LNB output with the the internal 22 kHz tone. Since the I
2
C
interface is compatible with the 400 kHz transfer speed, this
bit may be used to encode DiSEqC 2.0 tone bursts for
communication with the LNB or switcher at the far end of
the coaxial cable.
Status Register (I
2
C Read Register)
. The main fault
conditions: overcurrent, undervoltage, and overtemperature,
are all indicated by setting the relevant bit in the Status
register. In all fault cases, once the bit is set it is not reset
until the A8285/A8287 is read by the I
2
C master. The cur-
rent status of the LNB output is also indicated by DIS. DIS
and PNG are the only bits that may be reset without an I
2
C
read sequence. The normal sequence of the master in a fault
condition is to detect the fault by reading the Status register,
then rereading the Status register until the status bit is reset,
indicating the fault condition has been reset. The fault may
be detected by: continuously polling, responding to an inter-
rupt request (IRQ), or detecting a fault condition externally
and performing a diagnostic poll of all slave devices. Note
that the fully operational condition of the Status register is
all 0s. This simpli
fi
es checking of the status byte.
Bit 0 (TSD)
. A 1 indicates that the A8285/A8287 has
detected an overtemperature condition and has disabled
the LNB output. DIS is set and the A8285/A8287 does not
re-enable the output until so instructed by writing the rel-
evant bit into the Control register. The status of the overtem-
perature condition is sampled on the rising edge of the ninth
clock pulse in the data read sequence. If the condition is no
longer present, then the TSD bit is reset, allowing the master
to re-enable the LNB output if required. If the condition is
still present, then the TSD bit remains at 1.
Bit 1 (OCP) Overcurrent
. If the A8285/A8287 detects an
overcurrent condition for greater than the detection time, and
if ODT is enabled, the LNB output is then disabled. Also, the
OCP bit is set to indicate that an overcurrent has occurred,
and the DIS bit is set. The Status register is updated on the
rising edge of the ninth clock pulse. The OCP bit is reset in
all cases, allowing the master to re-enable the LNB output. If
the overcurrent timer is not enabled, the A8285/A8287 oper-
ates in current limit inde
fi
nitely, and the OCP bit is not set.
Bit 2 and 3.
Reserved.
Bit 4 (PNG) Power Not Good
. Set to 1 when the LNB
output is enabled and the LNB output volts are below 85%
of the programmed LNB voltage. The PNG is reset when the
LNB volts are within 90% of the programmed LNB voltage.
Bit 5 (DIS) LNB output disabled
. DIS is used to indicate
the current condition of the LNB output. At power-on, or if
a fault condition occurs, the disable bit is set. Having this bit
change to 1 does not cause the IRQ to activate because the
LNB output may be disabled intentionally by the I
2
C master.
This bit also is reset at the end of a write sequence, if the
LNB output is enabled.
Bit 6.
Reserved.
Bit 7 (VUV) Undervoltage lockout.
Set to 1 to indicate that
the A8285/A8287 has detected that the input supply V
IN
is, or
has been, below the minimum level and that an undervoltage
lockout has occurred, which has disabled the LNB output.
Bit 5 also is set, and the A8285/A8287 does not re-enable the
output until so instructed (by having the relevant bit written
into the Control register). The status of the undervoltage con-
dition is sampled on the rising edge of the ninth clock pulse
in the data read sequence. If the condition is no longer pres-
ent, the VUV bit is reset, allowing the master to re-enable the
LNB output if required. If the condition is still present, the
VUV bit remains set to 1.
Control (I
2
C Write) Register Table
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A8285SLB | LNB Supply and Control Voltage Regulator |
| A82DL1624UG-70UF | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL16x4T(U) 16 Megabit (2Mx8 Bit/1Simultaneous Operation Flash Memory and 4M (256Kx16 Bit) S |
| A82DL1634UG-70 | LED Lamp; Bulb Size:3mm; LED Color:Red; Luminous Intensity:1.6ucd; Viewing Angle:60 ; Forward Current:2mA; Forward Voltage:1.7V; Operating Temperature Range:-55 C to ? C; Color:Red; Leaded Process Compatible:No RoHS Compliant: No |
| A82DL1634TG-70IF | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL16x4T(U) 16 Megabit (2Mx8 Bit/1Simultaneous Operation Flash Memory and 4M (256Kx16 Bit) S |
| A82DL1644TG-70IF | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL16x4T(U) 16 Megabit (2Mx8 Bit/1Simultaneous Operation Flash Memory and 4M (256Kx16 Bit) S |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A8287SLB | 功能描述:IC REG LNB SUPPLY/CTRL 24-SOIC RoHS:否 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - 專用型 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,000 系列:- 應用:電源，ICERA E400，E450 輸入電壓:4.1 V ~ 5.5 V 輸出數(shù):10 輸出電壓:可編程 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:42-WFBGA，WLCSP 供應商設備封裝:42-WLP 包裝:帶卷 (TR) |
| A8287SLB-T | 制造商:Allegro MicroSystems LLC 功能描述: |
| A8287SLBTR | 功能描述:IC REG LNB SUPPLY/CTRL 24-SOIC RoHS:否 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - 專用型 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,000 系列:- 應用:電源，ICERA E400，E450 輸入電壓:4.1 V ~ 5.5 V 輸出數(shù):10 輸出電壓:可編程 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:42-WFBGA，WLCSP 供應商設備封裝:42-WLP 包裝:帶卷 (TR) |
| A8287SLBTR-T | 功能描述:IC LNB SUPPLY/VOLTAGE REG 24SOIC RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - 專用型 系列:- 標準包裝:2,000 系列:- 應用:控制器，DSP 輸入電壓:4.5 V ~ 25 V 輸出數(shù):2 輸出電壓:最低可調(diào)至 1.2V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:30-TFSOP（0.173"，4.40mm 寬） 供應商設備封裝:30-TSSOP 包裝:帶卷 (TR) |
| A8290 | 制造商:ALLEGRO 制造商全稱:Allegro MicroSystems 功能描述:Single LNB Supply and Control Voltage Regulator |
發(fā)布緊急采購，3分鐘左右您將得到回復。