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參數資料
| 型號： | a8251 |
| 廠商： | Altera Corporation |
| 英文描述： | Programmable Communications Interface(可編程通信接口) |
| 中文描述： | 可編程通信接口（可編程通信接口） |
| 文件頁數： | 9/21頁 |
| 文件大小： | 338K |
| 代理商： | A8251 |
Altera Corporation
33
a8251 Programmable Communications Interface Data Sheet
Note:
(1)
A
pe
,
oe
, or
fe
error signal can be cleared by a total state reset (see
“Reset
Operation” section on page 42
), by an internal state reset, or by writing a logic high
to bit 4 (
er
) of the command instruction register.
Sync Character One Register
The sync character one register holds the first sync character. The
information is used by the receiver for sync comparison and by the
transmitter for sync character transmission.
Table 9. Status Register Format
Data
Bit
Signal Name
Function
0
Transmitter ready
(
txrdy
)
Indicates that the transmitter is ready to
receive another data byte. Unlike the
corresponding output, this bit is not conditional
upon the
cts
input and the
txen
command
bit.
Bit 1 reflects the state of the
rxrdy
signal.
Bit 2 reflects the state of the
txempty
signal.
1
2
Receiver ready (
rxrdy
)
Transmitter empty
(
txempty
)
Parity error (
pe
)
Note (1)
3
When high, bit 3 indicates that the parity bit
received over the
rxd
input does not match
the parity calculated by the receiver. If no
parity has been selected, this error will not
occur.
Bit 4 indicates that data was ready to write into
the RBR before the previous contents of the
register were read by the microprocessor.
Bit 5 is set when a received character does not
end with the expected number of stop bits,
which is usually caused by a transmission
error.
Bit 6 reflects the state of the
syn_brk
output.
4
Overrun error (
oe
)
Note (1)
5
Framing error (
fe
)
Note (1)
6
Sync or break detect
(
syn_brk
)
Data set ready (
dsr
)
7
Bit 7 reflects the logical inverse of the state of
the
ndsr
input.
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