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參數(shù)資料
| 型號： | a8251 |
| 廠商： | Altera Corporation |
| 英文描述： | Programmable Communications Interface(可編程通信接口) |
| 中文描述： | 可編程通信接口（可編程通信接口） |
| 文件頁數(shù)： | 18/21頁 |
| 文件大?。?/td> | 338K |
| 代理商： | A8251 |
42
Altera Corporation
a8251 Programmable Communications Interface Data Sheet
Figure 8. Transmitter Control Signals (Synchronous)
The X indicates “don’t care.”
The
txrdy
and
txempty
signals function identically when programmed
for asynchronous or synchronous operation. However, when the
transmitter becomes empty, the
a8251
automatically inserts sync
characters into the data stream. If the
scs
signal is high, a single sync
character is inserted. Otherwise, two sync characters are inserted.
Reset Operation
The
a8251
is reset in one of two ways:
I
I
Total state reset
Internal state reset
Total state reset is an asynchronous operation achieved by asserting the
reset
input. All internal registers and control logic are asynchronously
reset to their initial state.
Internal state reset is achieved by writing a logic high into bit 6 (
ir
) of the
command instruction register, which resets all internal registers and
control logic to their initial state. Internal state reset occurs synchronously
to the rising edge of the
clk
signal. The master clock signal (
clk
) must be
running to achieve an internal state reset.
Sync Characters
One
Two
Parity Bit
Parity Bit
Parity Bit
txd
ncts
txempty
txrdy
(Status Bit)
txrdy
(Pin)
X
X
X
X
X
cnd
nwr
Sync Characters
One
Two
Data Characters
One
Two
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