- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄378264 > A80960HT75SL2GP (INTEL CORP) 80960HA/HD/HT 32-Bit High-Performance Superscalar Processor PDF資料下載
參數(shù)資料
| 型號： | A80960HT75SL2GP |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 80960HA/HD/HT 32-Bit High-Performance Superscalar Processor |
| 中文描述： | 32-BIT, 75 MHz, RISC PROCESSOR, CPGA168 |
| 封裝： | PGA-168 |
| 文件頁數(shù)： | 17/102頁 |
| 文件大?。?/td> | 828K |
| 代理商： | A80960HT75SL2GP |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁當前第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁
80960HA/HD/HT
Advance Information
Datasheet
11
CLKIN
I
CLOCK INPUT
provides the time base for the 80960Hx. All internal circuitry is
synchronized to CLKIN. All input and output timings are specified relative to
CLKIN.
For the 80960HD, the 2x internal clock is derived by multiplying the CLKIN
frequency by 2. For the 80960HT, the 3x internal clock is derived by multiplying
the CLKIN frequency by 3.
RESET
I
A(L)
RESET
forces the device into reset. RESET causes all external and internal
signals to return to their reset state (if defined). The rising edge of RESET starts
the processor boot sequence.
STEST
I
S(L)
SELF TEST
, when asserted during the rising edge of RESET, causes the
processor to execute its built in self-test.
FAIL
O
H(Q)
B(Q)
R(0)
FAIL
indicates a failure of the processor’s built-in self-test performed during
initialization. FAIL is asserted immediately out of reset and toggles during self-test
to indicate the status of individual tests. If self-test passes, FAIL is de-asserted
and the processor branches to the user’s initialization code. When self-test fails,
the FAIL pin asserts and the processor ceases execution.
ONCE
I
ON-CIRCUIT EMULATION
control: the processor samples this pin during reset. If
it is asserted low at the end of reset, the processor enters ONCE mode. In ONCE
mode, the processor stops all clocks and floats all output pins except the TDO pin.
ONCE uses an internal pull-up resistor; see R
definition in
Table 21 “80960Hx
DC Characteristics” on page 32
. Pull this pin high when not in use.
TCK
I
TEST CLOCK
provides the clocking function for IEEE 1149.1 Boundary Scan
testing.
TDI
I
TEST DATA INPUT
is the serial input pin for IEEE 1149.1 Boundary Scan testing.
TDI uses an internal pull-up resistor; see R
PU
definition in
Table 21 “80960Hx DC
Characteristics” on page 32
.
TDO
O
TEST DATA OUTPUT
is the serial output pin for IEEE 1149.1 Boundary Scan
testing. ONCE does not disable this pin.
TRST
I
TEST RESET
asynchronously resets the Test Access Port (TAP) controller. TRST
must be held low at least 10,000 clock cycles after power-up. One method is to
provide TRST with a separate power-on-reset circuit. TRST includes an internal
pull-up resistor; see R
definition in
Table 21 “80960Hx DC Characteristics” on
page 32
. Pull this pin low when not in use.
TMS
I
TEST MODE SELECT
is sampled at the rising edge of TCK. TCK controls the
sequence of TAP controller state changes for IEEE 1149.1 Boundary Scan
testing. TMS uses an internal pull-up resistor; see R
PU
definition in
Table 21
“80960Hx DC Characteristics” on page 32
.
VCC5
I
5 V REFERENCE VOLTAGE
input is the reference voltage for the 5 V-tolerant I/O
buffers. Connect this signal to +5 V for use with inputs which exceed 3.3 V. When
all inputs are from 3.3 V components, connect this signal to 3.3 V.
VCCPLL
I
PLL VOLTAGE
is the +3.3 VDC analog input for the PLL.
VOLDET
O
VOLTAGE DETECT
signal allows external system logic to distinguish between a
5 V 80960Cx processor and the 3.3 V 80960Hx processor. This signal is active
low for a 3.3 V 80960Hx (it is high impedance for 5 V 80960Cx). This pin is
available only on the PGA version.
0 = 80960Hx
1 = 80960Cx
Table 7.
80960Hx Processor Family Pin Descriptions (Sheet 4 of 4)
Name
Type
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A80960HA25SL2GX | 80960HA/HD/HT 32-Bit High-Performance Superscalar Processor |
| A80960HA40SL2GZ | 80960HA/HD/HT 32-Bit High-Performance Superscalar Processor |
| A80960HA33SL2GY | 80960HA/HD/HT 32-Bit High-Performance Superscalar Processor |
| A80960HD32SL2GG | 80960HA/HD/HT 32-Bit High-Performance Superscalar Processor |
| A80960HD50SL2GH | 80960HA/HD/HT 32-Bit High-Performance Superscalar Processor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A80960JA-16 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:EMBEDDED 32-BIT MICROPROCESSOR |
| A80960JA-25 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:EMBEDDED 32-BIT MICROPROCESSOR |
| A80960JA-33 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:EMBEDDED 32-BIT MICROPROCESSOR |
| A80960JA3V25 | 功能描述:IC MPU I960JA 3V 25MHZ 132-PGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標準包裝:60 系列:SCC 處理器類型:Z380 特點:全靜電 Z380 CPU 速度:20MHz 電壓:5V 安裝類型:表面貼裝 封裝/外殼:144-LQFP 供應(yīng)商設(shè)備封裝:144-LQFP 包裝:托盤 |
| A80960JA3V33 | 功能描述:IC MPU I960JA 3V 33MHZ 132-PGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標準包裝:40 系列:MPC83xx 處理器類型:32-位 MPC83xx PowerQUICC II Pro 特點:- 速度:267MHz 電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 封裝/外殼:516-BBGA 裸露焊盤 供應(yīng)商設(shè)備封裝:516-PBGAPGE（27x27） 包裝:托盤 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。