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參數(shù)資料
| 型號： | A63L73321 |
| 廠商： | AMIC Technology Corporation |
| 元件分類： | 通用總線功能 |
| 英文描述： | 128K X 32 Bit Synchronous High Speed SRAM with Burst Counter and Flow-through Data Output |
| 中文描述： | 128K的× 32位同步計數(shù)器高的Burst SRAM的速度和流量，通過數(shù)據(jù)輸出 |
| 文件頁數(shù)： | 2/17頁 |
| 文件大小： | 186K |
| 代理商： | A63L73321 |
A63L73321
Preliminary
128K X 32 Bit Synchronous High Speed SRAM
with Burst Counter and Flow-through Data Output
PRELIMINARY (August, 2000, Version 0.4)
1
AMIC Technology, Inc.
Features
n
Fast access times: 12ns at 66MHz
n
Single +3.3V+10% or +3.3V-5% power supply
n
Synchronous burst function
n
Individual Byte Write control and Global Write
n
Double-cycle enable, single-cycle deselect
General Description
The A63L73321 is a high-speed, low-power SRAM
containing 4,194,304 bits of bit synchronous memory,
organized as 131,072 words by 32 bits.
The A63L73321 combines advanced synchronous
peripheral circuitry, 2-bit burst control, input registers,
output buffer and a 128K X 32 SRAM core to provide a
wide range of data RAM applications.
The positive edge triggered single clock input (CLK)
controls all synchronous inputs passing through the
registers. Synchronous inputs include all addresses (A0 -
A16), all data inputs (I/O
1
- I/O
32
), active LOW chip enable
( CE ), two additional chip enables (CE2, CE2 ), burst
control inputs ( ADSC , ADSP , ADV ), byte write
enables (BWE , BW1, BW2 , BW3 , BW4 ) and Global
Write (GW ). Asynchronous inputs include output enable
( OE ), clock (CLK), BURST mode (MODE) and SLEEP
mode (ZZ).
n
Three separate chip enables allow wide range of
options for CE control, address pipelining
n
Selectable BURST mode
n
SLEEP mode (ZZ pin) provided
n
Available in 100-pin LQFP package
Burst operations can be initiated with either the address
status processor ( ADSP ) or address status controller
( ADSC ) input pin. Subsequent burst sequence burst
addresses can be internally generated by the A63L73321
and controlled by the burst advance ( ADV ) pin. Write
cycles are internally self-timed and synchronous with the
rising edge of the clock (CLK).
This feature simplifies the write interface. Individual Byte
enables allow individual bytes to be written. BW1
controls I/O
1
- I/O
8
, BW2 controls I/O
9
- I/O
16
, BW3
controls I/O
17
- I/O
24
, and BW4 controls I/O
25
- I/O
32
, all
on the condition that BWE is LOW. GW LOW causes
all bytes to be written.
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| A63L7332E-45 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:128K X 32 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output |
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