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參數(shù)資料
| 型號(hào)： | A63L73321 |
| 廠商： | AMIC Technology Corporation |
| 元件分類： | 通用總線功能 |
| 英文描述： | 128K X 32 Bit Synchronous High Speed SRAM with Burst Counter and Flow-through Data Output |
| 中文描述： | 128K的× 32位同步計(jì)數(shù)器高的Burst SRAM的速度和流量，通過(guò)數(shù)據(jù)輸出 |
| 文件頁(yè)數(shù)： | 10/17頁(yè) |
| 文件大?。?/td> | 186K |
| 代理商： | A63L73321 |
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A63L73321
PRELIMINARY (August, 2000, Version 0.4)
9
AMIC Technology, Inc.
AC Characteristics
(0
°
C
≤
T
A
≤
70
°
C, VCC = 3.3V+10% or 3.3V-5%)
Symbol
Parameter
-12
Unit
Note
Min.
Max.
t
KC
Clock Cycle Time
15
-
ns
t
KH
Clock High Time
4.0
-
ns
t
KL
Clock Low Time
4.0
-
ns
t
KQ
Clock to Output Valid
-
12
ns
t
KQX
Clock to Output Invalid
3.0
-
ns
t
KQLZ
Clock to Output in Low-Z
4.0
-
ns
5, 6
t
KQHZ
Clock to Output in High-Z
-
5.0
ns
5, 6
t
OEQ
OE to Output Valid
-
5.0
ns
8
t
OELZ
OE to Output in Low-Z
0
-
ns
5, 6
t
OEHZ
OE to Output in High-Z
-
5.0
ns
5, 6
Setup Times
t
AS
Address
2.5
-
ns
7, 9
t
ADSS
Address Status ( ADSC , ADSP )
2.5
-
ns
7, 9
t
ADVS
Address Advance ( ADV )
2.5
-
ns
7, 9
t
WS
Write Signals
(BW1, BW2 , BW3 , BW4 , BWE , GW )
2.5
-
ns
7, 9
t
DS
Data-in
2.5
-
ns
7, 9
t
CES
Chip Enable (CE, CE2, CE2 )
2.5
-
ns
7, 9
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A63L73321E-12 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:128K X 32 Bit Synchronous High Speed SRAM with Burst Counter and Flow-through Data Output |
| A63L73321SERIES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:128K X 32 Bit Synchronous High Speed SRAM with Burst Counter and Flow-through Data Output |
| A63L7332E-42 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:128K X 32 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output |
| A63L7332E-45 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:128K X 32 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output |
| A63L7332E-5 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:128K X 32 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output |
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