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參數(shù)資料
| 型號： | A54SXxx |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | FPGA |
| 英文描述： | 54SX Family FPGAs |
| 中文描述： | 54SX家庭的FPGA |
| 文件頁數(shù)： | 9/57頁 |
| 文件大小： | 415K |
| 代理商： | A54SXXX |
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v3.1
9
5 4 S X F a m ily F P G A s
S X P robe C irc uit C ont rol P ins
The Silicon Explorer II tool uses the boundary scan ports
(TDI, TCK, TMS and TDO) to select the desired nets for
verification. The selected internal nets are assigned to the
PRA/PRB pins for observation.
Figure7
illustrates the
interconnection between Silicon Explorer II and the FPGA
to perform in-circuit verification. The TRST pin is equipped
with a pull-up resistor. To remove the boundary scan state
machine from the reset state during probing, it is
recommended that the TRST pin be left floating.
De s ig n C ons ide ra t ions
The TDI, TCK, TDO, PRA, and PRB pins should not be used
as input or bidirectional ports. Because these pins are
active during probing, critical signals input through these
pins are not available while probing. In addition, the
Security Fuse should not be programmed because doing so
disables the Probe Circuitry.
Figure 7
Probe Setup
SX FPGA
TDI
TCK
TMS
TDO
PRA
PRB
Serial Connection
1
C
Silicon Explorer II
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