Figure 2-6 Input Buffer Delays PAD Y INBUF In 3 V 0" />
參數(shù)資料
型號(hào): A54SX72A-PQ208A
廠商: Microsemi SoC
文件頁(yè)數(shù): 39/108頁(yè)
文件大?。?/td> 0K
描述: IC FPGA SX-A 108K 208-PQFP
標(biāo)準(zhǔn)包裝: 24
系列: SX-A
LAB/CLB數(shù): 6036
輸入/輸出數(shù): 171
門(mén)數(shù): 108000
電源電壓: 2.25 V ~ 5.25 V
安裝類(lèi)型: 表面貼裝
工作溫度: -40°C ~ 125°C
封裝/外殼: 208-BFQFP
供應(yīng)商設(shè)備封裝: 208-PQFP(28x28)
SX-A Family FPGAs
2- 16
v5.3
Input Buffer Delays
C-Cell Delays
Cell Timing Characteristics
Figure 2-6 Input Buffer Delays
PAD
Y
INBUF
In
3 V
0 V
1.5 V
Out
GND
50%
1.5 V
50%
VCC
t
INY
t
INY
Figure 2-7 C-Cell Delays
S
A
B
Y
S, A, or B
Out
GND
50%
Out
GND
50%
V
CC
V
CC
V
CC
t
PD
t
PD
t
PD
t
PD
Figure 2-8 Flip-Flops
(Positive Edge Triggered)
D
CLK
CLR
Q
D
CLK
Q
CLR
t
HPWH
t
WASYN
t
HD
t
SUD
t
HP
t
HPWL
t
RCO
t
CLR
t
RPWL
t
RPWH
PRESET
tPRESET
PRESET
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