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參數(shù)資料
| 型號： | A54SX72A-BG208B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Hex inverters with open collector outputs 14-PDIP 0 to 70 |
| 中文描述： | 的SX - A系列FPGA的 |
| 文件頁數(shù)： | 24/108頁 |
| 文件大?。?/td> | 720K |
| 代理商： | A54SX72A-BG208B |
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SX-A Family FPGAs
2-4
v5.1
Table 2-8
AC Specifications (5 V PCI Operation)
Symbol
Parameter
Condition
Min.
Max.
Units
I
OH(AC)
Switching Current High
0 < V
OUT
≤
1.4
1
1.4
≤
V
OUT
< 2.4
1, 2
3.1 < V
OUT
< V
CCI
1, 3
–44
–
mA
(–44 + (V
OUT
– 1.4)/0.024)
–
mA
–
EQ 2-1 on
page 2-5
–
(Test Point)
V
OUT
= 3.1
3
V
OUT
≥
2.2
1
2.2 > V
OUT
> 0.55
1
0.71 > V
OUT
> 0
1, 3
–
–142
mA
I
OL(AC)
Switching Current Low
95
–
mA
(V
OUT
/0.023)
–
mA
–
EQ 2-2 on
page 2-5
–
(Test Point)
V
OUT
= 0.71
3
–5 < V
IN
≤
–1
0.4 V to 2.4 V load
4
–
206
mA
I
CL
Low Clamp Current
–25 + (V
IN
+ 1)/0.015
–
mA
slew
R
Output Rise Slew Rate
1
5
V/ns
slew
F
Output Fall Slew Rate
2.4 V to 0.4 V load
4
1
5
V/ns
Notes:
1. Refer to the V/I curves in
Figure 2-1 on page 2-5
. Switching current characteristics for REQ# and GNT# are permitted to be one half
of that specified here; i.e., half size output drivers may be used on these signals. This specification does not apply to CLK and RST#,
which are system outputs. “Switching Current High” specifications are not relevant to SERR#, INTA#, INTB#, INTC#, and INTD#,
which are open drain outputs.
2. Note that this segment of the minimum current curve is drawn from the AC drive point directly to the DC drive point rather than
toward the voltage rail (as is done in the pull-down curve). This difference is intended to allow for an optional N-channel pull-up.
3. Maximum current requirements must be met as drivers pull beyond the last step voltage. Equations defining these maximums (A
and B) are provided with the respective diagrams in
Figure 2-1 on page 2-5
. The equation defined maximum should be met by
design. In order to facilitate component testing, a maximum current test point is defined for each side of the output driver.
4. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any
point within the transition range. The specified load (diagram below) is optional; i.e., the designer may elect to meet this parameter
with an unloaded output per revision 2.0 of the PCI Local Bus Specification. However, adherence to both maximum and minimum
parameters is now required (the maximum is no longer simply a guideline). Since adherence to the maximum slew rate was not
required prior to revision 2.1 of the specification, there may be components in the market for some time that have faster edge
rates; therefore, motherboard designers must bear in mind that rise and fall times faster than this specification could occur and
should ensure that signal integrity modeling accounts for this. Rise slew rate does not apply to open drain outputs.
Output
Buffer
1/2 in. max.
50 pF
Pin
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|---|---|
| A54SX72A-BG208I | SX-A Family FPGAs |
| A54SX72A-BG208M | Hex inverters with open collector outputs 14-PDIP 0 to 70 |
| A54SX72A-CQ208 | Hex inverters with open collector outputs 14-SO 0 to 70 |
| A54SX72A-CQ208A | Hex inverters with open collector outputs 14-SO 0 to 70 |
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