參數(shù)資料
型號: A54SX16-3TQ208PP
廠商: Electronic Theatre Controls, Inc.
英文描述: LM199/LM299/LM399 Precision Reference
中文描述: 54SX家庭的FPGA
文件頁數(shù): 2/57頁
文件大?。?/td> 415K
代理商: A54SX16-3TQ208PP
5 4 S X F a m ily F P G A s
2
v3.1
G e ne ra l De s c ript ion
Actel’s SX family of FPGAs features a sea-of-modules
architecture that delivers device performance and
integration levels not currently achieved by any other FPGA
architecture. SX devices greatly simplify design time, enable
dramatic reductions in design costs and power
consumption, and further decrease time to market for
performance-intensive applications.
Actel’s SX architecture features two types of logic modules,
the combinatorial cell (C-cell) and the register cell (R-cell),
each optimized for fast and efficient mapping of synthesized
logic functions. The routing and interconnect resources are
in the metal layers above the logic modules, providing
optimal use of silicon. This enables the entire floor of the
device to be spanned with an uninterrupted grid of
fine-grained,
synthesis-friendly
“sea-of-modules”), which reduces the distance signals have
to travel between logic modules. To minimize signal
propagation delay, SX devices employ both local and general
routing resources. The high-speed local routing resources
(DirectConnect and FastConnect) enable very fast local
signal propagation that is optimal for fast counters, state
logic
modules
(or
machines, and datapath logic. The general system of
segmented routing tracks allows any logic module in the
array to be connected to any other logic or I/O module.
Within this system, propagation delay is minimized by
limiting the number of antifuse interconnect elements to
five (90percent of connections typically use only three
antifuses). The unique local and general routing structure
featured in SX devices gives fast and predictable
performance, allows 100percent pin-locking with full logic
utilization, enables concurrent PCB development, reduces
design time, and allows designers to achieve performance
goals with minimum effort.
Further complementing SX’s flexible routing structure is a
hard-wired, constantly loaded clock network that has been
tuned to provide fast clock propagation with minimal clock
skew. Additionally, the high performance of the internal
logic has eliminated the need to embed latches or flip-flops
in the I/O cells to achieve fast clock-to-out or fast input
set-up times. SX devices have easy-to-use I/O cells that do
not require HDL instantiation, facilitating design re-use and
reducing design and verification time.
Orde ring Inform a t ion
Application (Temperature Range)
Blank = Commercial (0 to +70°C)
I = Industrial (–40 to +85°C)
M = Military (–55 to +125°C)
PP = Pre-production
Package Type
BG = Ball Grid Array
PL = Plastic Leaded Chip Carrier
PQ
=
Plastic Quad Flat Pack
TQ = Thin (1.4 mm) Quad Flat Pack
VQ = Very Thin (1.0 mm) Quad Flat Pack
FG = Fine Pitch Ball Grid Array (1.0 mm)
Speed Grade
Blank = Standard Speed
–1
=
Approximately 15% Faster than Standard
–2
=
Approximately 25% Faster than Standard
–3 = Approximately 35% Faster than Standard
Part Number
A54SX08
A
54SX
16
A54SX16P = 24,000
System
Gates
A
54SX
32
=
48,000 System Gates
= 12,000 System Gates
= 24,000 System Gates
Package Lead Count
A54SX16
PQ
208
2
Blank = Not PCI Compliant
P
=
PCI Compliant
P
相關(guān)PDF資料
PDF描述
A54SX16-3VQ208 54SX Family FPGAs
A54SX16-3VQ208I LM199/LM299/LM399 Precision Reference; Package: TO-46; No of Pins: 4
A54SX16-3VQ208M 54SX Family FPGAs
A54SX16-3VQ208PP LM19 2.4V, 10μA, TO-92 Temperature Sensor; Package: TO-92; No of Pins: 3; Qty per Container: 1800; Container: Box
A54SX16-BG208 54SX Family FPGAs
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