參數(shù)資料
型號(hào)： A54SX08A-2FG144I
廠商： Microsemi SoC
文件頁(yè)數(shù)： 76/108頁(yè)
文件大?。?/td> 0K
描述： IC FPGA SX 12K GATES 144-FBGA
標(biāo)準(zhǔn)包裝： 160
系列： SX-A
LAB/CLB數(shù)： 768
輸入/輸出數(shù)： 111
門數(shù)： 12000
電源電壓： 2.25 V ~ 5.25 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 85°C
封裝/外殼： 144-LBGA
供應(yīng)商設(shè)備封裝： 144-FPBGA（13x13）
SX-A Family FPGAs
v5.3
1-3
Routing Resources
The routing and interconnect resources of SX-A devices
are in the top two metal layers above the logic modules
(Figure 1-1 on page 1-1), providing optimal use of silicon,
thus enabling the entire floor of the device to be
spanned with an uninterrupted grid of logic modules.
Interconnection between these logic modules is achieved
using the Actel patented metal-to-metal programmable
antifuse
interconnect
elements.
The
antifuses
are
normally open circuits and, when programmed, form a
permanent low-impedance connection.
Clusters and SuperClusters can be connected through the
use of two innovative local routing resources called
FastConnect and DirectConnect, which enable extremely
fast and predictable interconnection of modules within
Clusters and SuperClusters (Figure 1-5 on page 1-4 and
Figure 1-6 on page 1-4). This routing architecture also
dramatically reduces the number of antifuses required to
complete
a
circuit,
ensuring
the
highest
possible
performance, which is often required in applications such
as fast counters, state machines, and data path logic. The
interconnect elements (i.e., the antifuses and metal
tracks) have lower capacitance and lower resistance than
any other device of similar capacity, leading to the fastest
signal propagation in the industry.
DirectConnect is a horizontal routing resource that
provides connections from a C-cell to its neighboring
R-Cell in a given SuperCluster. DirectConnect uses a
hardwired signal path requiring no programmable
interconnection to achieve its fast signal propagation
time of less than 0.1 ns.
FastConnect enables horizontal routing between any
two logic modules within a given SuperCluster, and
vertical routing with the SuperCluster immediately
below it. Only one programmable connection is used in a
FastConnect path, delivering a maximum pin-to-pin
propagation time of 0.3 ns.
In addition to DirectConnect and FastConnect, the
architecture makes use of two globally oriented routing
resources known as segmented routing and high-drive
routing. The Actel segmented routing structure provides
a variety of track lengths for extremely fast routing
between SuperClusters. The exact combination of track
lengths and antifuses within each path is chosen by the
100% automatic place-and-route software to minimize
signal propagation delays.
The general system of routing tracks allows any logic
module in the array to be connected to any other logic
or I/O module. Within this system, most connections
typically require three or fewer antifuses, resulting in
fast and predictable performance.
The unique local and general routing structure featured
in SX-A devices allows 100% pin-locking with full logic
utilization, enables concurrent printed circuit board
(PCB) development, reduces design time, and allows
designers to achieve performance goals with minimum
effort.
Figure 1-4 Cluster Organization
Type 1 SuperCluster
Type 2 SuperCluster
Cluster 1
Cluster 2
Cluster 1
R-Cell
C-Cell
D0
D1
D2
D3
DB
A0 B0
A1 B1
Sa
Sb
Y
DirectConnect
Input
CLKA,
CLKB,
Internal Logic
HCLK
CKS
CKP
CLR
PRE
Y
DQ
Routed
Data Input
S0
S1
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