參數(shù)資料
型號(hào)： A54SX08-TQ176I
廠商： Microsemi SoC
文件頁(yè)數(shù)： 14/64頁(yè)
文件大?。?/td> 0K
描述： IC FPGA SX 12K GATES 176-TQFP
標(biāo)準(zhǔn)包裝： 40
系列： SX
LAB/CLB數(shù)： 768
輸入/輸出數(shù)： 128
門(mén)數(shù)： 12000
電源電壓： 3 V ~ 3.6 V，4.75 V ~ 5.25 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 85°C
封裝/外殼： 176-LQFP
供應(yīng)商設(shè)備封裝： 176-TQFP（24x24）
SX Family FPGAs
v3.2
1-17
shows
capacitance
values
for
various
devices.
Guidelines for Calculating Power
Consumption
The power consumption guidelines are meant to
represent worst-case scenarios so that they can be
generally used to predict the upper limits of power
dissipation. These guidelines are shown in Table 1-14.
Sample Power Calculation
One of the designs used to characterize the SX family
was a 528 bit serial-in, serial-out shift register. The design
utilized 100 percent of the dedicated flip-flops of an
A54SX16P device. A pattern of 0101… was clocked into
the device at frequencies ranging from 1 MHz to
200 MHz. Shifting in a series of 0101… caused 50 percent
of the flip-flops to toggle from low to high at every clock
cycle.
Follow the steps below to estimate power consumption.
The values provided for the sample calculation below are
for the shift register design above. This method for
estimating power consumption is conservative and the
actual power consumption of your design may be less
than the estimated power consumption.
The total power dissipation for the SX family is the sum
of the AC power dissipation and the DC power
dissipation.
PTotal = PAC (dynamic power) + PDC (static power)
EQ 1-9
AC Power Dissipation
PAC = PModule + PRCLKA Net + PRCLKB Net + PHCLK Net +
POutput Buffer + PInput Buffer
EQ 1-10
PAC = VCCA
2 × [(m × C
EQM × fm)Module +
(n × CEQI × fn)Input Buffer+ (p × (CEQO + CL) × fp)Output Buffer +
(0.5 (q1 × CEQCR × fq1) + (r1 × fq1))RCLKA +
(0.5 (q2 × CEQCR × fq2)+ (r2 × fq2))RCLKB +
(0.5 (s1 × CEQHV × fs1) + (CEQHF × fs1))HCLK]
EQ 1-11
Table 1-13 Capacitance Values for Devices
A54SX08
A54SX16
A54SX16P A54SX32
CEQM (pF)
4.0
CEQI (pF)
3.4
CEQO (pF)
4.7
CEQCR (pF)
1.6
CEQHV
0.615
CEQHF
60
96
140
r1 (pF)
87
138
171
r2 (pF)
87
138
171
Table 1-14 Power Consumption Guidelines
Description
Power Consumption Guideline
Logic Modules (m)
20% of modules
Inputs Switching (n)
# inputs/4
Outputs Switching (p)
# outputs/4
First Routed Array Clock Loads (q1)
20% of register cells
Second Routed Array Clock Loads (q2)
20% of register cells
Load Capacitance (CL)
35 pF
Average Logic Module Switching Rate (fm)
f/10
Average Input Switching Rate (fn)
f/5
Average Output Switching Rate (fp)
f/10
Average First Routed Array Clock Rate (fq1)
f/2
Average Second Routed Array Clock Rate (fq2)
f/2
Average Dedicated Array Clock Rate (fs1)
f
Dedicated Clock Array Clock Loads (s1)
20% of regular modules
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