參數(shù)資料
型號(hào)： A49LF004TX-33C
廠商： AMIC Technology Corporation
英文描述： 4 Mbit CMOS 3.3Volt-only Firmware Hub Flash Memory
中文描述： 4兆位的CMOS 3.3Volt只閃存固件集線器
文件頁(yè)數(shù)： 11/32頁(yè)
文件大?。?/td> 595K
代理商： A49LF004TX-33C
A49LF004
PRELIMINARY (November, 2003, Version 0.0)
10
AMIC Technology, Corp.
Table 6: Lock Register Bit Definition
ADDRESS/ADDRESS MULTIPLEXED (A/A
MUX) MODE
Device Operation
Commands are used to initiate the memory operation
functions of the device. The data portion of the software
command sequence is latched on the rising edge of WE#.
During the software command sequence the row address is
latched on the falling edge of R/C# and the column address
is latched on the rising edge of R/C#. Refer to Table 7 and
Table 8 for operation modes and the command sequence.
Read
The Read operation of the A49LF004 device is controlled by
OE#. OE# is the output control and is used to gate data from
the output pins. Refer to the Read cycle timing diagram,
Figure 10 for further details.
Reset
A V
IL
on RST# pin initiates a device reset.
Byte-Program Operation
The A49LF004 device is programmed on a byte-by-byte
basis. Before programming, one must ensure that the block,
in which the byte which is being programmed exists, is fully
erased. The Byte-Program operation is initiated by executing
a four-byte command load sequence for Software Data
Protection with address and data in the last byte sequence.
During the Byte-Program operation, the row address (A10-
A0) is latched on the falling edge of R/C# and the column
Address (A21-A11) is latched on the rising edge of R/C#.
The data bus is latched in the rising edge of WE#. See
Figure 11 for Program operation timing diagram, Figure 14
for timing waveforms, and Figure 19 for its flowchart. During
the Program operation, the only valid reads are Data#
Polling and Toggle Bit. During the internal Program
operation, the host is free to perform additional tasks. Any
commands written during the internal Program operation will
be ignored.
Data
Reserved
Bit 7:3
Read-Lock
Bit 2
Lock-Down
Bit 1
Write-Lock
Bit 0
Function
00h
00000
0
0
0
Full Access.
01h
00000
0
0
1
Write locked. Default state at power-up.
02h
00000
0
1
0
Locked open (full access locked down).
03h
00000
0
1
1
Write-locked down.
04h
00000
1
0
0
Read locked.
05h
00000
1
0
1
Read and Write locked.
06h
00000
1
1
0
Read-locked down
07h
00000
1
1
1
Read- and Write-locked down
Data
Function
7:3
Reserved
Read-Lock
1 = Prevents read operations in the block where set
0 = Normal operation for reads in the block where clear. This is the default state.
Lock-Down
1 = Prevents further set or clear operations to the Write-Lock and Read-Lock bits. Lock-Down only can be set
but not clear. The block will remain lock-down until reset (with RST# or INIT# being Low), or until the device
is power-on reset.
0 = Normal operation for Write-Lock and Read-Lock bit altering in the block where clear. This is the default state.
Write-Lock
1 = Prevents program or erase operations in the block where set. This is the default state.
0 = Normal operation for programming and erase in the block where clear.
2
1
0
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