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參數(shù)資料
| 型號： | A49LF004 |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | 4 Mbit CMOS 3.3Volt-only Firmware Hub Flash Memory |
| 中文描述： | 4兆位的CMOS 3.3Volt只閃存固件集線器 |
| 文件頁數(shù)： | 6/32頁 |
| 文件大?。?/td> | 595K |
| 代理商： | A49LF004 |
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ABSOLUTE MAXIMUM RATINGS*
A49LF004
PRELIMINARY (November, 2003, Version 0.0)
5
AMIC Technology, Corp.
Temperature Under Bias . . . . . . . . . . . . . -55
°
C to + 125
°
C
Storage Temperature . . . . . . . . . . . . . . . . . -65
°
C to + 125
°
C
D.C. Voltage on Any Pins with Respect to Ground
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD + 0.5V
Package Power Dissipation Capability (Ta=25
°
C)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD + 0.5V
Output Short Circuit Current
. . . . . . . . . . . . . . . . 50mA
Notes:
1. Minimum DC voltage on input or I/O pins is -0.5V. During
voltage transitions, input or I/O pins may undershoot VSS to -
2.0V for periods of up to 20ns. Maximum DC voltage on input
and I/O pins is VDD + 0.5V. During voltage transitions, input or
I/O pins may
overshoot to VDD + 2.0V for periods up to 20ns.
2. No more than one output is shorted at a time. Duration of the
short circuit should not be greater than one second.
*Comments
Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to this device. These are stress
ratings only. Functional operation of this device at these or any
other conditions above those indicated in the operational sections of
these specifications are not implied or intended. Exposure to the
absolute maximum rating conditions for extended periods may
affect device reliability.
Operating Ranges
Commercial (C) Devices
Ambient Temperature (T
A
) . . . . . . . . . . . . . . 0
°
C to +85
°
C
VDD Supply Voltages
VDD for all devices . . . . . . . . . . . . . . . . . . +3.0V to +3.6V
Operating ranges define those limits between which the
functionally of the device is guaranteed.
MODE SELECTION
The A49LF004 flash memory devices can operate in two
distinct interface modes: the Firmware Hub Interface
(FWH) mode and the Address/Address Multiplexed (A/A
Mux) mode. The IC (Interface Configuration pin) is used to
set the interface mode selection. If the IC pin is set to logic
High, the device is in A/A Mux mode; while if the IC pin is set
Low, the device is in the FWH mode. The IC selection pin
must be configured prior to device operation. The IC pin is
internally pulled down if the pin is not connected. In FWH
mode, the device is configured to interface with its host
using
Intel’s
Firmware
Hub
Communication between Host and the A49LF004 occurs via
the 4-bit I/O communication signals, FWH [3:0] and the
FWH4. In A/A Mux mode, the device is programmed via an
11-bit address A
10
-A
0
and an 8-bit data I/O
7
-I/O
0
parallel
signals. The address inputs are multiplexed in row and
column selected by control signal R/C# pin. The column
addresses are mapped to the higher internal addresses, and
the row addresses are mapped to the lower internal
addresses. See the Device Memory Maps in Figure 3 for
address assignment.
proprietary
protocol.
FWH MODE OPERATION
The FWH interface consists of four data signals (FWH[3:0]),
one control signal (FWH4) and a clock (CLK). The data
signals, control signal and clock comply with PCI
specifications. Operations such as Memory Read and
Memory Write use Intel FWH propriety protocol. JEDEC
Standard SDP (Software Data Protection) Byte-Program and
Block-Erase command sequences are incorporated into the
FWH memory cycles. Chip-Erase command is only available
in A/A Mux mode. The addresses and data are transferred
through FWH[3:0] synchronized with the input clock CLK
during a FWH memory cycle. The pulse of FWH4 is inserted
for at least one clock period to indicate the start of a FWH
memory cycle. The address or data on FWH[3:0] is latched
on the rising edge of CLK. The device enters standby mode
when FWH4 is high and no internal operation is in progress.
The device is in ready mode when FWH4 is low and no
activity is on the FWH bus.
FWH Read Operation
FWH Read operations read from the memory cells or
specific registers in the FWH device. A valid FWH Read
operation starts when FWH4 is Low as CLK rises and a
START value “1101b” is on FWH[3:0]. Addresses and data
are transferred to and from the device decided by a series of
“fields”. Field sequences and contents are strictly defined for
FWH Read operations. Refer to Table 2 for FWH Read
Cycle Definition.
FWH Write Operation
FWH Write operations write to the FWH Interface or FWH
registers. A valid FWH Write operation starts when FWH4 is
Low as CLK rises and a START value “1110b” is on
FWH[3:0]. Addresses and data are transferred to and from
the device decided by a series of “fields”. Field sequences
and contents are strictly defined for FWH Write operations.
Refer to Table 3 for FWH write Cycle Definition.
FWH Abort Operation
If FWH4 is driven low for one or more clock cycles during a
FWH cycle, the cycle will be terminated and the device will
wait for the ABORT command. The host may drive the
FWH[3:0] with ‘1111b’ (ABORT command) to return the
device to Ready mode. If abort occurs during a Write
operation, the data may be incorrectly altered.
Response To Invalid Fields
During FWH operations, the FWH will not explicitly indicate
that it has received invalid field sequences. The response to
specific invalid fields or sequences is as follows:
Address out of range:
The FWH address sequence is 7
fields long (28 bits), but only the last five address fields
(20 bits) will be decoded by A49LF004. Address A22 has the
special function of directing reads and writes to the flash
memory (A22=1) or to the register space (A22=0).
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