
A49FL004 
4 Mbit CMOS 3.3Volt-only Firmware Hub/LPC Flash Memory  
Preliminary  
PRELIMINARY       (September, 2005, Version 0.0) 
1 
AMIC Technology, Corp.
FEATURES 
 Single Power Supply Operation                       
- 
Low voltage range: 3.0 V - 3.6 V  
 Standard Intel Firmware Hub/LPC Interface 
- 
Read compatible to Intel 82802 Firmware 
Hub devices 
- 
Conforms to Intel LPC Interface Specification  
Revision 1.1 
 Memory Configuration
- 
512K x 8 (4 Mbit) 
 
Block Architecture
- 
Uniform 4 KBytes Sectors  
- 
Uniform 64 KByte overlay blocks 
- 
Support full chip erase for Address/Address 
Multiplexed (A/A Mux) mode 
 
Automatic Erase and Program Operation 
- 
Build-in automatic program verification for extended 
product endurance 
- 
Typical 10 μs/byte programming time 
- 
Typical x s sector erase time  
- 
Typical y s block erase time 
- 
Typical z s chip erase time 
 Two Configurable Interfaces 
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In-System hardware interface: Auto detection of 
Firmware Hub (FWH) or Low Pin Count (LPC) 
Interface for in-system read and write operations 
- 
Address/Address Multiplexed (A/A Mux) Interface for 
programming on EPROM Programmers during 
manufacturing 
 Firmware Hub (FWH)/Low Pin Count (LPC) Mode 
- 
33 MHz synchronous operation with PCI bus 
- 
5-signal communication interface for in-system read 
and write operations 
- 
- 
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-      Register-based read and write protection for 
each block 
- 
4 ID pins for multiple chips selection  
- 
5 GPI pins for General Purpose Input Register 
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TBL
 pin for hardware write protection to Boot Block 
- 
WP
 pin for hardware write protection to whole memory 
array except Boot Block 
 Address/Address Multiplexed (A/A Mux) Mode                               
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11-pin multiplexed address and 8-pin data I/O interface 
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Supports fast programming on EPROM programmers 
- 
Standard SDP Command Set 
- 
DataPolling and Toggle Bit features 
 Lower Power Consumption 
- 
Typical 12mA active read current 
- 
Typical 17mA program/erase current 
 
High Product Endurance 
- 
Guarantee 100,000 program/erase cycles per single 
sector (preliminary) 
- 
Minimum 20 years data retention 
 Compatible Pin-out and Packaging 
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32-pin (8 mm x 14 mm) TSOP  
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32-pin PLCC 
- 
Optional lead-free (Pb-free) package 
 Hardware Data Protection
Standard SDP Command Set 
DataPolling and Toggle Bit features 
Block Locking Register for all blocks