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參數(shù)資料
| 型號： | A43E06321G-95F |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | 512K X 32 Bit X 2 Banks Low Power Synchronous DRAM |
| 中文描述： | 為512k × 32位× 2銀行低功耗同步DRAM |
| 文件頁數(shù)： | 6/46頁 |
| 文件大小： | 1351K |
| 代理商： | A43E06321G-95F |
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A43E06321
PRELIMINARY
(July, 2005, Version 0.0)
5
AMIC Technology, Corp.
Decoupling Capacitance Guide Line
Recommended decoupling capacitance added to power line at board
Parameter
Symbol
Value
Unit
Decoupling Capacitance between VDD and VSS
C
DC1
0.1 + 0.01
μ
F
Decoupling Capacitance between VDDQ and VSSQ
C
DC2
0.1 + 0.01
μ
F
Note:
1. VDD and VDDQ pins are separated each other.
All VDD pins are connected in chip. All VDDQ pins are connected in chip.
2. VSS and VSSQ pins are separated each other
All VSS pins are connected in chip. All VSSQ pins are connected in chip.
DC Electrical Characteristics
(Recommended operating condition unless otherwise noted, T
A
= 0oC to +70oC for commercial or T
A
= -40oC to +85oC for extended)
Speed
Symbol
Parameter
Test Conditions
-75
-95
Units
Note
I
cc1
Operating Current
(One Bank Active)
Burst Length = 1
t
RC
≥
t
RC
(min), t
CC
≥
t
CC
(min
)
, I
OL
= 0mA
40
mA
1
I
cc2
P
CKE
≤
V
IL
(max), t
CC
= 15ns
0.3
I
cc2
PS
Precharge Standby Current
in power-down mode
CKE
≤
V
IL
(max), t
CC
=
∞
0.5
mA
I
CC2
N
CKE
≥
V
IH
(min),
CS
≥
V
IH
(min), t
CC
= 15ns
Input signals are changed one time during 30ns
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
Input signals are stable.
5.5
I
CC2
NS
Precharge Standby Current
in non power-down mode
2
mA
I
CC3
P
CKE
≤
V
IL
(max), t
CC
= 15ns
1.5
I
CC3
N
Active Standby current in
non power-down mode
(One Bank Active)
CKE
≥
V
IH
(min),
CS
≥
V
IH
(min), t
CC
= 15ns
Input signals are changed one time during 30ns
12
mA
I
CC4
Operating Current
(Burst Mode)
I
OL
= 0mA, Page Burst
All bank Activated, t
CCD
= t
CCD
(min)
45
mA
1
I
CC5
Refresh Current
t
RC
≥
t
RC
(min)
60
mA
2
2 Banks
100
I
CC6
Self Refresh Current
CKE
≤
0.2V
1 Banks
80
uA
I
CC7
Deep Power Down Current
CKE
≤
0.2V
10
uA
Note:
1. Measured with outputs open. Addresses are changed only one time during t
CC
(min).
2. Refresh period is 64ms. Addresses are changed only one time during t
CC
(min).
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| A43E06321G-95UF | 512K X 32 Bit X 2 Banks Low Power Synchronous DRAM |
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相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A43E06321G-95UF | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:512K X 32 Bit X 2 Banks Low Power Synchronous DRAM |
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| A43E0632V-75I | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:1M X 16 Bit X 4 Banks Synchronous DRAM |
| A43E0632V-95I | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:1M X 16 Bit X 4 Banks Synchronous DRAM |
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