參數(shù)資料
型號: A43E06321G-95F
廠商: AMIC Technology Corporation
英文描述: 512K X 32 Bit X 2 Banks Low Power Synchronous DRAM
中文描述: 為512k × 32位× 2銀行低功耗同步DRAM
文件頁數(shù): 38/46頁
文件大?。?/td> 1351K
代理商: A43E06321G-95F
A43E06321
PRELIMINARY (July, 2005, Version 0.0)
37
AMIC Technology, Corp.
Self Refresh Entry & Exit Cycle
* Note : TO ENTER SELF REFRESH MODE
1.
CS
,
RAS
&
CAS
with CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don’t care except for CKE.
3. The device remains in self refresh mode as long as CKE stays “Low”.
(cf.) Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh.
TO EXIT SELF REFRESH MODE
4. System clock restart and be stable before returning CKE high.
5.
CS
starts from high.
6. Minimum tRC is required after CKE going high to complete self refresh exit.
7. Before/After self refresh mode, AUTO REFRESH commands must be issued every 15.6
μ
s or less as both SELF
REFRESH and AUTO REFRESH utilize the row refresh counter.
0
1
2
3
4
5
6
7
8
9
10
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13
14
15
16
17
18
19
CLOCK
CKE
CS
RAS
CAS
ADDR
BA
: Don't care
A10/AP
WE
Self Refresh Exit
Auto Refresh
DQM
DQ
Self Refresh Entry
t
SS
* Note 4
* Note 1
~
t
RC min.
~
~
~
~
* Note 3
* Note 2
~
t
SS
* Note 6
~
~
* Note 5
~
~
* Note 7
* Note 7
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
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~
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~
Hi-Z
Hi-Z
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