tDLH Data-to-Pad HIGH 3.5" />
參數(shù)資料
型號： A42MX16-FVQ100
廠商： Microsemi SoC
文件頁數(shù)： 111/142頁
文件大小： 0K
描述： IC FPGA MX SGL CHIP 24K 100-VQFP
標(biāo)準(zhǔn)包裝： 90
系列： MX
輸入/輸出數(shù)： 83
門數(shù)： 24000
電源電壓： 3 V ~ 3.6 V，4.75 V ~ 5.25 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 70°C
封裝/外殼： 100-TQFP
供應(yīng)商設(shè)備封裝： 100-VQFP（14x14）
40MX and 42MX FPGA Families
1- 66
R e v i sio n 1 1
TTL Output Module Timing5
tDLH
Data-to-Pad HIGH
3.5
3.9
4.4
5.2
7.3
ns
tDHL
Data-to-Pad LOW
4.1
4.6
5.2
6.1
8.6
ns
tENZH
Enable Pad Z to HIGH
3.8
4.2
4.8
5.6
7.8
ns
tENZL
Enable Pad Z to LOW
4.2
4.6
5.3
6.2
8.7
ns
tENHZ
Enable Pad HIGH to Z
7.6
8.4
9.5
11.2
15.7
ns
tENLZ
Enable Pad LOW to Z
7.0
7.8
8.8
10.4
14.5
ns
tGLH
G-to-Pad HIGH
4.8
5.3
6.0
7.2
10.0
ns
tGHL
G-to-Pad LOW
4.8
5.3
6.0
7.2
10.0
ns
tLCO
I/O Latch Clock-to-Out
(Pad-to-Pad), 64 Clock Loading
8.0
8.9
10.1
11.9
16.7
ns
tACO
Array Clock-to-Out
(Pad-to-Pad), 64 Clock Loading
11.3
12.5
14.2
16.7
23.3
ns
dTLH
Capacitive Loading, LOW to HIGH
0.04
0.05
0.06
0.08 ns/pF
dTHL
Capacitive Loading, HIGH to LOW
0.05
0.06
0.07
0.10 ns/pF
CMOS Output Module Timing5
tDLH
Data-to-Pad HIGH
4.5
5.0
5.6
6.6
9.3
ns
tDHL
Data-to-Pad LOW
3.4
3.8
4.3
5.1
7.1
ns
tENZH
Enable Pad Z to HIGH
3.8
4.2
4.8
5.6
7.8
ns
tENZL
Enable Pad Z to LOW
4.2
4.6
5.3
6.2
8.7
ns
tENHZ
Enable Pad HIGH to Z
7.6
8.4
9.5
11.2
15.7
ns
tENLZ
Enable Pad LOW to Z
7.0
7.8
8.8
10.4
14.5
ns
tGLH
G-to-Pad HIGH
7.1
7.9
8.9
10.5
14.7
ns
tGHL
G-to-Pad LOW
7.1
7.9
8.9
10.5
14.7
ns
tLCO
I/O Latch Clock-to-Out
(Pad-to-Pad), 64 Clock Loading
8.0
8.9
10.1
11.9
16.7
ns
tACO
Array Clock-to-Out
(Pad-to-Pad),64 Clock Loading
11.3
12.5
14.2
16.7
23.3
ns
dTLH
Capacitive Loading, LOW to HIGH
0.04
0.05
0.06
0.08 ns/pF
dTHL
Capacitive Loading, HIGH to LOW
0.05
0.06
0.07
0.10 ns/pF
Table 1-35 A42MX16 Timing Characteristics (Nominal 3.3 V Operation) (continued)
(Worst-Case Commercial Conditions, VCCA = 3.0 V, TJ = 70°C)
–3 Speed
–2 Speed
–1 Speed
Std Speed
–F Speed
Parameter / Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Notes:
1. For dual-module macros use tPD1 + tRD1 + taped, to + tRD1 + taped, or tPD1 + tRD1 + tusk, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External
setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external
PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
相關(guān)PDF資料
PDF描述
ASM30DTMI-S189 CONN EDGECARD 60POS R/A .156 SLD
A42MX16-FVQG100 IC FPGA MX SGL CHIP 24K 100-VQFP
ASM30DTAI-S189 CONN EDGECARD 60POS R/A .156 SLD
A40MX04-1PQ100I IC FPGA MX SGL CHIP 6K 100-PQFP
ASM30DTBI-S189 CONN EDGECARD 60POS R/A .156 SLD
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A42MX16-FVQ100A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-FVQ100B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-FVQ100ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-FVQ100I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-FVQ100M 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價(jià)

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*