參數(shù)資料
型號： A42MX16-FPQ100M
廠商： Electronic Theatre Controls, Inc.
英文描述： Octal Transparent D-Type Latches With 3-State Outputs 20-TSSOP -40 to 85
中文描述： 40MX和42MX FPGA系列
文件頁數(shù)： 49/123頁
文件大?。?/td> 854K
代理商： A42MX16-FPQ100M
40MX and 42MX FPGA Families
v6.0
1-43
Input Module Predicted Routing Delays
1
t
IRD1
FO=1 Routing Delay
2.1
2.4
2.2
3.2
4.5
ns
t
IRD2
FO=2 Routing Delay
2.6
3.0
3.4
4.0
5.6
ns
t
IRD3
FO=3 Routing Delay
3.1
3.6
4.1
4.8
6.7
ns
t
IRD4
FO=4 Routing Delay
3.6
4.2
4.8
5.6
7.8
ns
t
IRD8
Global Clock Network
FO=8 Routing Delay
5.7
6.6
7.5
8.8
12.4
ns
t
CKH
Input Low to HIGH
FO = 16
FO = 128
4.6
4.6
5.3
5.3
6.0
6.0
7.0
7.0
9.8
9.8
ns
t
CKL
Input High to LOW
FO = 16
FO = 128
4.8
4.8
5.6
5.6
6.3
6.3
7.4
7.4
10.4
10.4
ns
t
PWH
Minimum
Width HIGH
Pulse
FO = 16
FO = 128
2.2
2.4
2.6
2.7
2.9
3.1
3.4
3.6
4.8
5.1
ns
t
PWL
Minimum
Width LOW
Pulse
FO = 16
FO = 128
2.2
2.4
2.6
2.7
2.9
3.01
3.4
3.6
4.8
5.1
ns
t
CKSW
Maximum Skew
FO = 16
FO = 128
0.4
0.5
0.5
0.6
0.5
0.7
0.6
0.8
0.8
1.2
ns
t
P
Minimum Period
FO = 16
FO = 128
4.7
4.8
5.4
5.6
6.1
6.3
7.2
7.5
10.0
10.4
ns
f
MAX
Maximum
Frequency
FO = 16
FO = 128
188
181
175
168
160
154
139
134
83
80
MHz
TTL Output Module Timing
4
t
DLH
Data-to-Pad HIGH
3.3
3.8
4.3
5.1
7.2
ns
t
DHL
Data-to-Pad LOW
4.0
4.6
5.2
6.1
8.6
ns
t
ENZH
Enable Pad Z to HIGH
3.7
4.3
4.9
5.8
8.0
ns
t
ENZL
Enable Pad Z to LOW
4.7
5.4
6.1
7.2
10.1
ns
t
ENHZ
Enable Pad HIGH to Z
7.9
9.1
10.4
12.2
17.1
ns
t
ENLZ
Enable Pad LOW to Z
5.9
6.8
7.7
9.0
12.6
ns
d
TLH
Delta LOW to HIGH
0.02
0.02
0.03
0.03
0.04
ns/pF
d
THL
Delta HIGH to LOW
0.03
0.03
0.03
0.04
0.06
ns/pF
Table 30
A40MX04 Timing Characteristics (Nominal 5.0V Operation) (Continued)
(Worst-Case Commercial Conditions, V
CC
= 4.75V, T
J
= 70°C)
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Units
Parameter Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer utility from the Designer software to check the hold
time for this macro.
4. Delays based on 35 pF loading.
相關PDF資料
PDF描述
A42MX16-FTQ100 Octal Transparent D-Type Latches With 3-State Outputs 20-TSSOP -40 to 85
A42MX16-FTQ100A Octal Transparent D-Type Latches With 3-State Outputs 20-TSSOP -40 to 85
A42MX16-FTQ100B Octal Transparent D-Type Latches With 3-State Outputs 20-TSSOP -40 to 85
A42MX16-FTQ100ES Octal Transparent D-Type Latches With 3-State Outputs 20-TSSOP -40 to 85
A42MX16-FTQ100I Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs 20-SSOP -40 to 85
相關代理商/技術參數(shù)
參數(shù)描述
A42MX16-FPQ160 功能描述:IC FPGA MX SGL CHIP 24K 160-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標準包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計:36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應商設備封裝:256-FPBGA（17x17）
A42MX16-FPQ160I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
A42MX16-FPQ160M 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
A42MX16-FPQ208 功能描述:IC FPGA MX SGL CHIP 24K 208-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標準包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計:36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應商設備封裝:256-FPBGA（17x17）
A42MX16-FPQ208I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*