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參數(shù)資料
| 型號： | A42MX16-3PQ100 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 40MX and 42MX FPGA Families |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件頁數(shù)： | 4/120頁 |
| 文件大小： | 854K |
| 代理商： | A42MX16-3PQ100 |
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101
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
3.13.7
Timer3/Counter3
The 16-bit Timer/Counter unit allows accurate program execution timing (event management),
wave generation, and signal timing measurement. The main features are:
True 16-bit Design (i.e., allow a 16-bit PWM)
Eight Different Selectable Input Clocks for the Timer/Counter3
Two Independent Compare Units
Input Capture Noise Canceler
One Input Capture Unit with Noise Canceler
Clear Timer on Compare Match or Capture Event
Variable PWM Period
Frequency Generator
External Event Counter
Four Independent Interrupt Sources (T3CAP, T3COMA, T3COMB, T3OVF)
Figure 3-47. Timer3 Block Diagram
Timer3 consists of an 16-bit up counter with two compare registers (T3CORA, T3CORB) and
one capture register (T3ICR). The timer can be used as event counter, as timer and as signal
generator. Its output can be programmed as modulator. The two compare registers allow various
modes of signal generation and modulation. The counter can be driven by internal and external
clock sources. For the capture signals (T3ICP, CLK
T1, CLKT2, LFDO) it has a programmable
edge sensitive input with digital filtering unit (Noise Canceler) for reducing the chance of captur-
ing noise spikes. In the capture mode the counter value can be captured by a programmable
capture event from the internal Timer1 output (CLK
T1), Timer2 output (CLKT2), by an external
event (T3ICP), by the LF-Receiver output signal (LFDO) at the capture input pin or with a soft-
ware capture event by setting the T3SCE bit.
The special functionalities of this timer are the capture event trigger, re-start and single action
modes. In the single action mode the counter counts up once to the programmed compare
match value. These modes are very useful for modulation, signal generation, signal measure-
ment and phase controlling. Timer3 has a modulator output stage. As modulator or as sensor
measurement stage it works together with Timer2.
T3MRA
Edge detect
and
Noise canceler
16-bit Counter
MUX
Modulator
T3ICR
T3IMR
T3IFR
T3CAP
T3COMA
T3COMP
CL3
T2I
T3I
SCH
CLT
T3ICP
T3CPE
T3CRA
T3CRB
T3CORA
T3CORB
T3MRB
M2
CLKT3
CLKI/O
CLKT2
CLKT1
CLKT0
LFDO
CLKT1
CLKT2
T3OVF
T3O
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A42MX24-3PQ100 | 40MX and 42MX FPGA Families |
| A42MX36-3PQ100 | 40MX and 42MX FPGA Families |
| A42MX02-3PQ100A | 40MX and 42MX FPGA Families |
| A42MX04-3PQ100A | 40MX and 42MX FPGA Families |
| A42MX02-2CQ100 | 40MX and 42MX FPGA Families |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A42MX16-3PQ100A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3PQ100B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3PQ100ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3PQ100I | 功能描述:IC FPGA MX SGL CHIP 24K 100-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標準包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計:- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27） |
| A42MX16-3PQ100M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
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